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authorMichal Simek <michal.simek@xilinx.com>2021-07-30 08:00:10 +0200
committerMichal Simek <michal.simek@xilinx.com>2021-08-06 09:32:03 +0200
commit3f123b74242bc076ba6cae6d45a11bd5da1d977f (patch)
treef34e537b30687c2b5ddde77efc41f8f6dc58bbf3 /drivers/reset/reset-zynqmp.c
parent8396700c330d9149812192297a4418e0d5cc4409 (diff)
reset: zynqmp: Add reset controller for ZynqMP SoC
Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'drivers/reset/reset-zynqmp.c')
-rw-r--r--drivers/reset/reset-zynqmp.c100
1 files changed, 100 insertions, 0 deletions
diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
new file mode 100644
index 00000000000..57652346738
--- /dev/null
+++ b/drivers/reset/reset-zynqmp.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Xilinx, Inc. - Michal Simek
+ */
+
+#define LOG_CATEGORY UCLASS_RESET
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <reset-uclass.h>
+#include <zynqmp_firmware.h>
+
+#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
+#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
+
+struct zynqmp_reset_priv {
+ u32 reset_id;
+ u32 nr_reset;
+};
+
+static int zynqmp_pm_reset_assert(const u32 reset,
+ const enum zynqmp_pm_reset_action assert_flag)
+{
+ return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0,
+ NULL);
+}
+
+static int zynqmp_reset_assert(struct reset_ctl *rst)
+{
+ struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
+
+ dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
+
+ return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
+ PM_RESET_ACTION_ASSERT);
+}
+
+static int zynqmp_reset_deassert(struct reset_ctl *rst)
+{
+ struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
+
+ dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id);
+
+ return zynqmp_pm_reset_assert(priv->reset_id + rst->id,
+ PM_RESET_ACTION_RELEASE);
+}
+
+static int zynqmp_reset_request(struct reset_ctl *rst)
+{
+ struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
+
+ dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
+ rst, rst->id, priv->nr_reset);
+
+ if (rst->id > priv->nr_reset)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int zynqmp_reset_free(struct reset_ctl *rst)
+{
+ struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev);
+
+ dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__,
+ rst, rst->id, priv->nr_reset);
+
+ return 0;
+}
+
+static int zynqmp_reset_probe(struct udevice *dev)
+{
+ struct zynqmp_reset_priv *priv = dev_get_priv(dev);
+
+ priv->reset_id = ZYNQMP_RESET_ID;
+ priv->nr_reset = ZYNQMP_NR_RESETS;
+ return 0;
+}
+
+const struct reset_ops zynqmp_reset_ops = {
+ .request = zynqmp_reset_request,
+ .rfree = zynqmp_reset_free,
+ .rst_assert = zynqmp_reset_assert,
+ .rst_deassert = zynqmp_reset_deassert,
+};
+
+static const struct udevice_id zynqmp_reset_ids[] = {
+ { .compatible = "xlnx,zynqmp-reset" },
+ { }
+};
+
+U_BOOT_DRIVER(zynqmp_reset) = {
+ .name = "zynqmp_reset",
+ .id = UCLASS_RESET,
+ .of_match = zynqmp_reset_ids,
+ .ops = &zynqmp_reset_ops,
+ .probe = zynqmp_reset_probe,
+ .priv_auto = sizeof(struct zynqmp_reset_priv),
+};