diff options
author | Tom Rini <trini@konsulko.com> | 2024-10-09 09:02:22 -0600 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2024-10-09 09:02:22 -0600 |
commit | f8efc68b30e29360f7a419fe4968432179d7368b (patch) | |
tree | f7e4ed2b5d65eff2c81a16bf937eba4900f40543 /drivers/spi/atmel_spi.c | |
parent | fbe16bc28014dc1ed957f5fee7e53d6eee781aa9 (diff) | |
parent | 8be3beef44c29c70a9ec447a4f232f987e1b4c64 (diff) |
Merge patch series "spi-nor: Add parallel and stacked memories support"
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> says:
This series adds support for Xilinx qspi parallel and
stacked memeories.
In parallel mode, the current implementation assumes that a maximum
of two flashes are connected. The QSPI controller splits the data
evenly between both the flashes so, both the flashes that are connected
in parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->flags.
In stacked mode the current implementation assumes that a maximum of two
flashes are connected and both the flashes are of same make but can differ
in sizes. So, except the sizes all other flash parameters of both the flashes
are identical.
Spi-nor will pass on the appropriate flash select flag to low level driver,
and it will select pass all the data to that particular flash.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where addr
is the address specified by the user.
Similarly for read and erase operations it will read from both flashes, so
size and offset are divided by 2 and send to flash.
Diffstat (limited to 'drivers/spi/atmel_spi.c')
-rw-r--r-- | drivers/spi/atmel_spi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index 79f01001318..aaf3eddae42 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -125,7 +125,7 @@ static int atmel_spi_claim_bus(struct udevice *dev) struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); struct at91_spi *reg_base = bus_plat->regs; - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; u32 freq = priv->freq; u32 scbr, csrx, mode; @@ -174,7 +174,7 @@ static void atmel_spi_cs_activate(struct udevice *dev) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) return; @@ -189,7 +189,7 @@ static void atmel_spi_cs_deactivate(struct udevice *dev) struct udevice *bus = dev_get_parent(dev); struct atmel_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); - u32 cs = slave_plat->cs; + u32 cs = slave_plat->cs[0]; if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) return; |