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authorVenkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>2025-03-11 09:43:17 +0530
committerMichal Simek <michal.simek@amd.com>2025-04-16 13:42:06 +0200
commit3243f71b64db89b8a6c045d41379b65aceabdd3c (patch)
treec06e39949efb0d0c8d7daf72688f1c2695498f72 /drivers/spi/cadence_ospi_versal.c
parent5ffab6ee1279fe86ab21b529a04b1638a6664eaf (diff)
spi: cadence_ospi: Add device reset via OSPI controller
Add support for flash device reset via OSPI controller instead of using GPIO, as OSPI IP has device reset feature on Versal Gen2 platform. Also add compatible string for Versal Gen2 platform. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Link: https://lore.kernel.org/r/20250311041317.2992862-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/spi/cadence_ospi_versal.c')
-rw-r--r--drivers/spi/cadence_ospi_versal.c19
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 816916de16d..fbeb0c6a85c 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -204,3 +204,22 @@ void cadence_qspi_apb_enable_linear_mode(bool enable)
~VERSAL_OSPI_LINEAR_MODE, VERSAL_AXI_MUX_SEL);
}
}
+
+int cadence_device_reset(struct udevice *bus)
+{
+ struct cadence_spi_priv *priv = dev_get_priv(bus);
+ u32 reg;
+
+ reg = readl(priv->regbase + CQSPI_REG_CONFIG);
+ reg |= CQSPI_REG_CONFIG_RESET_CFG_FLD_MASK;
+ writel(reg, priv->regbase + CQSPI_REG_CONFIG);
+
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(5);
+ writel(reg | CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(150);
+ writel(reg & ~CQSPI_REG_CONFIG_RESET_PIN_FLD_MASK, priv->regbase + CQSPI_REG_CONFIG);
+ udelay(1200);
+
+ return 0;
+}