diff options
| author | Pratyush Yadav <p.yadav@ti.com> | 2021-06-26 00:47:09 +0530 |
|---|---|---|
| committer | Jagan Teki <jagan@amarulasolutions.com> | 2021-06-28 11:57:23 +0530 |
| commit | 38b0852b0eab1c5ce18ed8125572ffb0bb6973fd (patch) | |
| tree | fe3c7699258ee72efb052286c74db536a8d72af4 /drivers/spi/cadence_qspi.h | |
| parent | a6903aa7ea98872ff66424051f85cdf0178c86f8 (diff) | |
spi: cadence-qspi: Add support for octal DTR flashes
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not use
automatic write completion polling in DTR mode. Further, no write
completion polling makes it impossible to use DAC mode for DTR writes.
In that mode, the controller does not know beforehand how long a write
will be and so it can de-assert Chip Select (CS#) at any time. Once CS#
is de-assert, the flash will go into burning phase. But since the
controller does not do write completion polling, it does not know when
the flash is busy and might send in writes while the flash is not ready.
So, disable write completion polling and make writes go through indirect
mode for DTR writes and let spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'drivers/spi/cadence_qspi.h')
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 5c745541a6c..49b401168fc 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -36,6 +36,12 @@ struct cadence_spi_plat { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; + + /* Transaction protocol parameters. */ + u8 inst_width; + u8 addr_width; + u8 data_width; + bool dtr; }; struct cadence_spi_priv { @@ -59,9 +65,13 @@ void cadence_qspi_apb_controller_enable(void *reg_base_addr); void cadence_qspi_apb_controller_disable(void *reg_base_addr); void cadence_qspi_apb_dac_mode_enable(void *reg_base); -int cadence_qspi_apb_command_read(void *reg_base_addr, +int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat, const struct spi_mem_op *op); -int cadence_qspi_apb_command_write(void *reg_base_addr, +int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat, + const struct spi_mem_op *op); +int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat, const struct spi_mem_op *op); int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat, |