diff options
| author | Tom Rini <trini@konsulko.com> | 2023-05-09 12:45:49 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-05-09 12:45:49 -0400 |
| commit | 0a9a4384c1483a88776bca38e28f09be51161034 (patch) | |
| tree | c39e9bac9413c5c90f8da424865d67a7efdca315 /drivers/spi/spi-aspeed-smc.c | |
| parent | f1d33a44ca04fdca241c1d89fd79e2e56c930c7e (diff) | |
| parent | 716ed2a8c0bba085372df0eb7edb580b11e8d94c (diff) | |
Merge tag 'u-boot-rockchip-20230509' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Rockchip NFC driver update and dev addr pointer api update;
- use standard dr_mode for usb driver;
- rock pi boards dts update;
- Add rk3566 Anbernic boards;
- Misc fixes for drivers;
Diffstat (limited to 'drivers/spi/spi-aspeed-smc.c')
| -rw-r--r-- | drivers/spi/spi-aspeed-smc.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index 4b6ea9f8e96..39620310218 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -1125,17 +1125,16 @@ static int apseed_spi_of_to_plat(struct udevice *bus) int ret; struct clk hclk; - priv->regs = (void __iomem *)devfdt_get_addr_index(bus, 0); - if ((u32)priv->regs == FDT_ADDR_T_NONE) { + priv->regs = devfdt_get_addr_index_ptr(bus, 0); + if (!priv->regs) { dev_err(bus, "wrong ctrl base\n"); - return -ENODEV; + return -EINVAL; } - plat->ahb_base = - (void __iomem *)devfdt_get_addr_size_index(bus, 1, &plat->ahb_sz); - if ((u32)plat->ahb_base == FDT_ADDR_T_NONE) { + plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); + if (!plat->ahb_base) { dev_err(bus, "wrong AHB base\n"); - return -ENODEV; + return -EINVAL; } plat->max_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); @@ -1151,8 +1150,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) plat->hclk_rate = clk_get_rate(&hclk); clk_free(&hclk); - dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%lx\n", - (u32)priv->regs, plat->ahb_base, plat->ahb_sz); + dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", + (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n", plat->hclk_rate / 1000000, plat->max_cs); |