diff options
| author | Tom Rini <trini@konsulko.com> | 2015-12-18 07:28:24 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-12-18 07:28:24 -0500 |
| commit | 4832e17787acb29734d895751bc7a594908aecc6 (patch) | |
| tree | 74d28b656a3b31fd4053279535c13f1a808fb035 /drivers/spi/zynq_qspi.c | |
| parent | 123b70177931a5aed92beca76bb622b2f4005be8 (diff) | |
| parent | b5e9b9a9a1bb231e35e206f8f3e2becee1dd06ab (diff) | |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'drivers/spi/zynq_qspi.c')
| -rw-r--r-- | drivers/spi/zynq_qspi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 5825c6d8f1f..b98663c23b2 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ #define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */ +#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */ /* zynq qspi Transmit Data Register */ #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */ @@ -68,6 +69,9 @@ struct zynq_qspi_regs { u32 txd1r; /* 0x80 */ u32 txd2r; /* 0x84 */ u32 txd3r; /* 0x88 */ + u32 reserved1[5]; + u32 lqspicfg; /* 0xA0 */ + u32 lqspists; /* 0xA4 */ }; /* zynq qspi platform data */ @@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv) ZYNQ_QSPI_CR_MSTREN_MASK; writel(confr, ®s->cr); + /* Disable the LQSPI feature */ + confr = readl(®s->lqspicfg); + confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK; + writel(confr, ®s->lqspicfg); + /* Enable SPI */ writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr); } |