diff options
| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2024-09-26 10:25:05 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-09 09:01:54 -0600 |
| commit | 34da258bb0465de4bf44dc8949a9536cc06bf725 (patch) | |
| tree | 7aa92b21cd25503e3ad8ed496a38a3ef080546c1 /drivers/spi/zynq_spi.c | |
| parent | c480ec2c45b221b2044c6268c9773e78fa47f305 (diff) | |
spi: spi-uclass: Read chipselect and restrict capabilities
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat->cs[] array for later use.
Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable of handling it.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Diffstat (limited to 'drivers/spi/zynq_spi.c')
| -rw-r--r-- | drivers/spi/zynq_spi.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index d15d91a1d24..37fa12b96b5 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -240,15 +240,15 @@ static int zynq_spi_xfer(struct udevice *dev, unsigned int bitlen, u8 *rx_buf = din, buf; u32 ts, status; - debug("spi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n", - dev_seq(bus), slave_plat->cs, bitlen, len, flags); + debug("spi_xfer: bus:%i cs[0]:%i bitlen:%i len:%i flags:%lx\n", + dev_seq(bus), slave_plat->cs[0], bitlen, len, flags); if (bitlen % 8) { debug("spi_xfer: Non byte aligned SPI transfer\n"); return -1; } - priv->cs = slave_plat->cs; + priv->cs = slave_plat->cs[0]; if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev); |