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| author | Michal Simek <michal.simek@amd.com> | 2023-10-31 11:50:54 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-11-07 13:47:09 +0100 |
| commit | 1cd59c571cfc7f0c9813e64f81ca1d95380a7e22 (patch) | |
| tree | 14e4fd613f6f834c6c9f3744ed56b620f984fd9e /drivers/sysreset/sysreset-ti-sci.c | |
| parent | 83cab0b30fcb893a249d6644dd4e7cbe429e6750 (diff) | |
xilinx: versal: Setup 30MHz as default spi frequency
Align default SPI configuration with ZynqMP/Versal NET.
There is no reason to run on lower frequencies.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c1d6ebd659f3002649b1200c926f8b9ed3132085.1698749448.git.michal.simek@amd.com
Diffstat (limited to 'drivers/sysreset/sysreset-ti-sci.c')
0 files changed, 0 insertions, 0 deletions