diff options
| author | Chia-Wei Wang <chiawei_wang@aspeedtech.com> | 2024-09-10 17:39:16 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-09-11 20:35:03 +0800 |
| commit | 9efcb10a09d69d9cf14111dd452bbf54dc0502b4 (patch) | |
| tree | e1554ebe4da7d87915116f64d3264d9dd4e12714 /drivers/timer/ast_ibex_timer.c | |
| parent | 717002f8ff277bb687ce1f2739d0ef715d319ad9 (diff) | |
riscv: Add AST2700 SoC initial platform support
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU
for the first stage bootloader execution, namely SPL.
This patch implements the preliminary base to successfully run SPL
on this RV32-based MCU to the console banner message.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/timer/ast_ibex_timer.c')
0 files changed, 0 insertions, 0 deletions