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authorTom Rini <trini@konsulko.com>2020-09-30 09:21:43 -0400
committerTom Rini <trini@konsulko.com>2020-09-30 09:21:43 -0400
commit01114adfc1e0bf3cf5e2f3da858bb2c8e9810c1c (patch)
tree64ab9c9d1c2a5f3cc96b4c0fef1990cb73c1b356 /drivers/timer/riscv_timer.c
parent527fad0b2484bf1dd4c443c4c8f4384aa256938f (diff)
parent924de3216e9efdf1cdc71b8632099213aac03f2c (diff)
Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv into next
- Disable CMD_IRQ for RISC-V. - Update sipeed/maix doc - Obtain reg of SiFive RAM via dev_read_addr_index() instead of regmap API. - Cleans up RISC-V timer drivers and converts them to DM. - Correctly handle IPIs already pending upon prior stage bootloader (on the K210)
Diffstat (limited to 'drivers/timer/riscv_timer.c')
-rw-r--r--drivers/timer/riscv_timer.c39
1 files changed, 20 insertions, 19 deletions
diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 9f9f070e0b3..449fcfcfd59 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -1,36 +1,37 @@
// SPDX-License-Identifier: GPL-2.0+
/*
+ * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2018, Anup Patel <anup@brainfault.org>
+ * Copyright (C) 2012 Regents of the University of California
*
- * RISC-V privileged architecture defined generic timer driver
+ * RISC-V architecturally-defined generic timer driver
*
- * This driver relies on RISC-V platform codes to provide the essential API
- * riscv_get_time() which is supposed to return the timer counter as defined
- * by the RISC-V privileged architecture spec.
- *
- * This driver can be used in both M-mode and S-mode U-Boot.
+ * This driver provides generic timer support for S-mode U-Boot.
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <timer.h>
-#include <asm/io.h>
-
-/**
- * riscv_get_time() - get the timer counter
- *
- * Platform codes should provide this API in order to make this driver function.
- *
- * @time: the 64-bit timer count as defined by the RISC-V privileged
- * architecture spec.
- * @return: 0 on success, -ve on error.
- */
-extern int riscv_get_time(u64 *time);
+#include <asm/csr.h>
static int riscv_timer_get_count(struct udevice *dev, u64 *count)
{
- return riscv_get_time(count);
+ if (IS_ENABLED(CONFIG_64BIT)) {
+ *count = csr_read(CSR_TIME);
+ } else {
+ u32 hi, lo;
+
+ do {
+ hi = csr_read(CSR_TIMEH);
+ lo = csr_read(CSR_TIME);
+ } while (hi != csr_read(CSR_TIMEH));
+
+ *count = ((u64)hi << 32) | lo;
+ }
+
+ return 0;
}
static int riscv_timer_probe(struct udevice *dev)