diff options
| author | Neil Armstrong <neil.armstrong@linaro.org> | 2024-10-11 16:38:25 +0200 |
|---|---|---|
| committer | Mattijs Korpershoek <mkorpershoek@baylibre.com> | 2024-10-15 11:03:57 +0200 |
| commit | 502a50ab1f7e32e3e90056597e8ce6a0931789ba (patch) | |
| tree | e3382cdb91e640b648686a7de69c5f4109168bac /drivers/timer/tsc_timer.c | |
| parent | 1f12fc7e3350b179d17efaf5ba00fc3683cf33ec (diff) | |
usb: dwc3: fix dcache flush range calculation
The current flush operation will omit doing a flush/invalidate on
the first and last bytes if the base address and size are not aligned
with CACHELINE_SIZE.
This causes operation failures Qualcomm platforms.
Take in account the alignment and size of the buffer and also
flush the previous and last cacheline.
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Link: https://lore.kernel.org/r/20241011-u-boot-dwc3-gadget-dcache-fixup-v4-2-5f3498d8035b@linaro.org
Signed-off-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Diffstat (limited to 'drivers/timer/tsc_timer.c')
0 files changed, 0 insertions, 0 deletions