diff options
| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-10-27 11:31:59 +0530 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2022-11-03 13:27:56 +0800 |
| commit | ab1644bdc4d7083aea78e56ca58b72559a881a0f (patch) | |
| tree | f888102cea0ac0f4f25c954a3dca0966f8de344e /drivers/timer/xilinx-timer.c | |
| parent | a5dfa3b8a0f7ad555495bad1386613d2de4ba619 (diff) | |
riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers have been
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'drivers/timer/xilinx-timer.c')
0 files changed, 0 insertions, 0 deletions