Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next

- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral

2 files changed, 30 insertions, 3 deletions

diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 5f4bc6edb67..96cc49273f4 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -174,6 +174,29 @@ config X86_TSC_TIMER
 	help
 	  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 
+config X86_TSC_READ_BASE
+	bool "Read the TSC timer base on start-up"
+	depends on X86_TSC_TIMER
+	help
+	  On x86 platforms the TSC timer tick starts at the value 0 on reset.
+	  This it makes no sense to read the timer on boot and use that as the
+	  base, since we will miss some time taken to load U-Boot, etc. This
+	  delay is controlled by the SoC and we cannot reduce it, but for
+	  bootstage we want to record the time since reset as accurately as
+	  possible.
+
+	  The only exception is when U-Boot is used as a secondary bootloader,
+	  where this option should be enabled.
+
+config TPL_X86_TSC_TIMER_NATIVE
+	bool "x86 TSC timer uses native calibration"
+	depends on TPL && X86_TSC_TIMER
+	help
+	  Selects native timer calibration for TPL and don't include the other
+	  methods in the code. This helps to reduce code size in TPL and works
+	  on fairly modern Intel chips. Code-size reductions is about 700
+	  bytes.
+
 config MTK_TIMER
 	bool "MediaTek timer support"
 	depends on TIMER
diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c
index 0df551f94cc..43cb2d820e8 100644
--- a/drivers/timer/tsc_timer.c
+++ b/drivers/timer/tsc_timer.c
@@ -50,8 +50,7 @@ static unsigned long native_calibrate_tsc(void)
 		return 0;
 
 	crystal_freq = tsc_info.ecx / 1000;
-
-	if (!crystal_freq) {
+	if (!CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE) && !crystal_freq) {
 		switch (gd->arch.x86_model) {
 		case INTEL_FAM6_SKYLAKE_MOBILE:
 		case INTEL_FAM6_SKYLAKE_DESKTOP:
@@ -397,7 +396,8 @@ static void tsc_timer_ensure_setup(bool early)
 {
 	if (gd->arch.tsc_inited)
 		return;
-	gd->arch.tsc_base = rdtsc();
+	if (IS_ENABLED(CONFIG_X86_TSC_READ_BASE))
+		gd->arch.tsc_base = rdtsc();
 
 	if (!gd->arch.clock_rate) {
 		unsigned long fast_calibrate;
@@ -406,6 +406,10 @@ static void tsc_timer_ensure_setup(bool early)
 		if (fast_calibrate)
 			goto done;
 
+		/* Reduce code size by dropping other methods */
+		if (CONFIG_IS_ENABLED(X86_TSC_TIMER_NATIVE))
+			panic("no timer");
+
 		fast_calibrate = cpu_mhz_from_cpuid();
 		if (fast_calibrate)
 			goto done;