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| author | Zong Li <zong.li@sifive.com> | 2023-12-14 14:09:37 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-12-27 17:28:57 +0800 |
| commit | 40c76dfed29ac2173bd32d730979ef2531029048 (patch) | |
| tree | e481fe5e4eed432724f4891497b7c026cef938ec /drivers/usb/cdns3/core.c | |
| parent | 64e8482f1c94ab6e1fb4837a8744ca8a156c507e (diff) | |
riscv: cache: support cache enable in SPL stage
The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/usb/cdns3/core.c')
0 files changed, 0 insertions, 0 deletions