diff options
| author | Tom Rini <trini@konsulko.com> | 2021-08-10 16:17:55 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-08-30 14:10:05 -0400 |
| commit | 33e8e61694278c6e27d3bc28f96d74815e3aeed8 (patch) | |
| tree | 041976a80a475e0a0edf3da4eb770fc368c393c7 /drivers/usb/host/dwc2.h | |
| parent | 9b0583a839ab8b086b65b4762769abbe048a524d (diff) | |
usb: dwc2: Rename CONFIG_DWC2 namespace to DWC2
There are a number of DWC2 configuration options that are set in dwc2.h
and referenced in dwc2.c only. Move these out of the CONFIG_DWC2
namespace and in to the DWC2 namespace. Note that hikey was defining an
option that was already always enabled, so we can remove that hunk.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/usb/host/dwc2.h')
| -rw-r--r-- | drivers/usb/host/dwc2.h | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 97a06c48f21..a6f562fe60e 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -759,32 +759,32 @@ struct dwc2_core_regs { #define RH_B_PPCM 0xffff0000 /* port power control mask */ /* Default driver configuration */ -#define CONFIG_DWC2_DMA_ENABLE -#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ -#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ -#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ -#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) -#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ -#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ -#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 -#define CONFIG_DWC2_MAX_PACKET_COUNT 511 +#define DWC2_DMA_ENABLE +#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) +#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +#define DWC2_MAX_TRANSFER_SIZE 65535 +#define DWC2_MAX_PACKET_COUNT 511 #define DWC2_PHY_TYPE_FS 0 #define DWC2_PHY_TYPE_UTMI 1 #define DWC2_PHY_TYPE_ULPI 2 -#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ -#ifndef CONFIG_DWC2_UTMI_WIDTH -#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ +#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#ifndef DWC2_UTMI_WIDTH +#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ #endif -#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ -#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ -#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ -#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ -#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ -#undef CONFIG_DWC2_THR_CTL /* Threshold control */ -#define CONFIG_DWC2_TX_THR_LENGTH 64 -#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ +#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +#undef DWC2_I2C_ENABLE /* Enable I2C */ +#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +#undef DWC2_TS_DLINE /* External DLine pulsing */ +#undef DWC2_THR_CTL /* Threshold control */ +#define DWC2_TX_THR_LENGTH 64 +#undef DWC2_IC_USB_CAP /* IC Cap */ #endif /* __DWC2_H__ */ |