Merge branch '2023-05-02-assorted-platform-updates-and-additions'

- Updates for starqltechn and other qualcomm platforms, hi3798mv200,
  Broadcom Northstar, and mediatek platforms
- Drop omap5_uevm, and assorted TI platform updates
- Add MAX14526

14 files changed, 327 insertions, 20 deletions

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9101e538b09..75937fbb6d9 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -36,6 +36,8 @@ source "drivers/dfu/Kconfig"
 
 source "drivers/dma/Kconfig"
 
+source "drivers/extcon/Kconfig"
+
 source "drivers/fastboot/Kconfig"
 
 source "drivers/firmware/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 58be410135d..ed1e71c4d65 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)DM) += core/
 obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/
 obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
+obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/
 obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/
 obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/
 obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
new file mode 100644
index 00000000000..fbb73354aa3
--- /dev/null
+++ b/drivers/extcon/Kconfig
@@ -0,0 +1,31 @@
+menu "Extcon Support"
+
+config EXTCON
+	bool "External Connector Class (extcon) support"
+	depends on DM
+	help
+	  Say Y here to enable external connector class (extcon) support.
+	  This allows monitoring external connectors and supports external
+	  connectors with multiple states; i.e., an extcon that may have
+	  multiple cables attached. For example, an external connector
+	  of a device may be used to connect an HDMI cable and a AC adaptor,
+	  and to host USB ports. Many of 30-pin connectors including PDMI
+	  are also good examples.
+
+config EXTCON_SANDBOX
+	bool "Sandbox extcon"
+	depends on EXTCON
+	help
+	  Enable extcon support for sandbox. This is an emulation of a real
+	  extcon. Currectly all configuration is done in the probe.
+
+config EXTCON_MAX14526
+	bool "Maxim MAX14526 EXTCON Support"
+	depends on DM_I2C
+	depends on EXTCON
+	help
+	  If you say yes here you get support for the MUIC device of
+	  Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
+	  detector and switch.
+
+endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
new file mode 100644
index 00000000000..3309f2aac2e
--- /dev/null
+++ b/drivers/extcon/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_EXTCON) += extcon-uclass.o
+obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o
+obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c
new file mode 100644
index 00000000000..a33b5ef919c
--- /dev/null
+++ b/drivers/extcon/extcon-max14526.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <extcon.h>
+#include <asm/gpio.h>
+
+#define CONTROL_1	0x01
+#define SW_CONTROL	0x03
+
+#define ID_200		0x10
+#define ADC_EN		0x02
+#define CP_EN		0x01
+
+#define DP_USB		0x00
+#define DP_UART		0x08
+#define DP_AUDIO	0x10
+#define DP_OPEN		0x38
+
+#define DM_USB		0x00
+#define DM_UART		0x01
+#define DM_AUDIO	0x02
+#define DM_OPEN		0x07
+
+#define AP_USB		BIT(0)
+#define CP_USB		BIT(1)
+#define CP_UART		BIT(2)
+
+struct max14526_priv {
+	struct gpio_desc usif_gpio;
+	struct gpio_desc dp2t_gpio;
+	struct gpio_desc ifx_usb_vbus_gpio;
+};
+
+static void max14526_set_mode(struct udevice *dev, int mode)
+{
+	struct max14526_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if ((mode & AP_USB) || (mode & CP_USB)) {
+		/* Connect CP UART signals to AP */
+		ret = dm_gpio_set_value(&priv->usif_gpio, 0);
+		if (ret)
+			log_debug("cp-uart > ap failed (%d)\n", ret);
+	}
+
+	if (mode & CP_UART) {
+		/* Connect CP UART signals to DP2T */
+		ret = dm_gpio_set_value(&priv->usif_gpio, 1);
+		if (ret)
+			log_debug("cp-uart > dp2t failed (%d)\n", ret);
+	}
+
+	if (mode & CP_USB) {
+		/* Connect CP USB to MUIC UART */
+		ret = dm_gpio_set_value(&priv->ifx_usb_vbus_gpio, 1);
+		if (ret)
+			log_debug("usb-vbus-gpio enable failed (%d)\n", ret);
+
+		ret = dm_gpio_set_value(&priv->dp2t_gpio, 1);
+		if (ret)
+			log_debug("cp-usb > muic-uart failed (%d)\n", ret);
+	}
+
+	if ((mode & AP_USB) || (mode & CP_UART)) {
+		/* Connect CP UART to MUIC UART */
+		ret = dm_gpio_set_value(&priv->dp2t_gpio, 0);
+		if (ret)
+			log_debug("cp-uart > muic-uart failed (%d)\n", ret);
+	}
+
+	if (mode & AP_USB) {
+		/* Enables USB Path */
+		ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_USB | DM_USB);
+		if (ret)
+			log_debug("USB path set failed: %d\n", ret);
+	}
+
+	if ((mode & CP_USB) || (mode & CP_UART)) {
+		/* Enables UART Path */
+		ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_UART | DM_UART);
+		if (ret)
+			log_debug("UART path set failed: %d\n", ret);
+	}
+
+	/* Enables 200K, Charger Pump, and ADC */
+	ret = dm_i2c_reg_write(dev, CONTROL_1, ID_200 | ADC_EN | CP_EN);
+	if (ret)
+		log_debug("200K, Charger Pump, and ADC set failed: %d\n", ret);
+}
+
+static int max14526_probe(struct udevice *dev)
+{
+	struct max14526_priv *priv = dev_get_priv(dev);
+	int ret, mode = 0;
+
+	ret = gpio_request_by_name(dev, "usif-gpios", 0,
+				   &priv->usif_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("could not decode usif-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "dp2t-gpios", 0,
+				   &priv->dp2t_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("could not decode dp2t-gpios (%d)\n", ret);
+		return ret;
+	}
+
+	if (dev_read_bool(dev, "maxim,ap-usb"))
+		mode |= AP_USB;
+
+	if (dev_read_bool(dev, "maxim,cp-usb")) {
+		mode |= CP_USB;
+
+		ret = gpio_request_by_name(dev, "usb-vbus-gpios", 0,
+					   &priv->ifx_usb_vbus_gpio, GPIOD_IS_OUT);
+		if (ret) {
+			log_err("could not decode usb-vbus-gpios (%d)\n", ret);
+			return ret;
+		}
+	}
+
+	if (dev_read_bool(dev, "maxim,cp-uart"))
+		mode |= CP_UART;
+
+	max14526_set_mode(dev, mode);
+
+	return 0;
+}
+
+static const struct udevice_id max14526_ids[] = {
+	{ .compatible = "maxim,max14526-muic" },
+	{ }
+};
+
+U_BOOT_DRIVER(extcon_max14526) = {
+	.name		= "extcon_max14526",
+	.id		= UCLASS_EXTCON,
+	.of_match	= max14526_ids,
+	.probe		= max14526_probe,
+	.priv_auto	= sizeof(struct max14526_priv),
+};
diff --git a/drivers/extcon/extcon-sandbox.c b/drivers/extcon/extcon-sandbox.c
new file mode 100644
index 00000000000..ab6a6c1cfdc
--- /dev/null
+++ b/drivers/extcon/extcon-sandbox.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+
+static const struct udevice_id sandbox_extcon_ids[] = {
+	{ .compatible = "sandbox,extcon" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(extcon_sandbox) = {
+	.name		= "extcon_sandbox",
+	.id		= UCLASS_EXTCON,
+	.of_match	= sandbox_extcon_ids,
+};
diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c
new file mode 100644
index 00000000000..9dd22b57626
--- /dev/null
+++ b/drivers/extcon/extcon-uclass.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_EXTCON
+
+#include <common.h>
+#include <extcon.h>
+#include <dm.h>
+
+UCLASS_DRIVER(extcon) = {
+	.id			= UCLASS_EXTCON,
+	.name			= "extcon",
+	.per_device_plat_auto	= sizeof(struct extcon_uc_plat),
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4e1ae03e9fd..04460f1acb2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -511,6 +511,13 @@ config WINBOND_W83627
 	  legacy UART or other devices in the Winbond Super IO chips
 	  on X86 platforms.
 
+config QCOM_GENI_SE
+	bool "Qualcomm GENI Serial Engine Driver"
+	depends on ARCH_SNAPDRAGON
+	help
+	  The driver manages Generic Interface (GENI) firmware based
+	  Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
+
 config QFW
 	bool
 	help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3b792f2a14c..52aed096021 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_P2SB) += p2sb-uclass.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
 ifdef CONFIG_QFW
 obj-y += qfw.o
 obj-$(CONFIG_QFW_PIO) += qfw_pio.o
diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c
new file mode 100644
index 00000000000..281a5ec819a
--- /dev/null
+++ b/drivers/misc/qcom-geni-se.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
+ *
+ * Copyright (C) 2023 Linaro Ltd. <vladimir.zapolskiy@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/io.h>
+
+static int geni_se_qup_read(struct udevice *dev, int offset,
+			    void *buf, int size)
+{
+	fdt_addr_t base = dev_read_addr(dev);
+
+	if (size != sizeof(u32))
+		return -EINVAL;
+
+	*(u32 *)buf = readl(base + offset);
+
+	return size;
+}
+
+static struct misc_ops geni_se_qup_ops = {
+	.read = geni_se_qup_read,
+};
+
+static const struct udevice_id geni_se_qup_ids[] = {
+	{ .compatible = "qcom,geni-se-qup" },
+	{}
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+	.name = "geni_se_qup",
+	.id = UCLASS_MISC,
+	.of_match = geni_se_qup_ids,
+	.ops = &geni_se_qup_ops,
+	.flags  = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index 2cec5b9ae32..71962cd47e0 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -100,6 +100,8 @@ static const struct udevice_id hi6220_dwmmc_ids[] = {
 	  .data = (ulong)&hi6220_mmc_data },
 	{ .compatible = "hisilicon,hi3798cv200-dw-mshc",
 	  .data = (ulong)&hi6220_mmc_data },
+	{ .compatible = "hisilicon,hi3798mv200-dw-mshc",
+	  .data = (ulong)&hi6220_mmc_data },
 	{ .compatible = "hisilicon,hi3660-dw-mshc",
 	  .data = (ulong)&hi3660_mmc_data },
 	{ }
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 47e2d67426f..5a4d58b3272 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -349,10 +349,10 @@ int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, bool disable,
 {
 	int err;
 
-	/* try pupd_r1_r0 if pullen_pullsel return error */
+	/* set pupd_r1_r0 if pullen_pullsel succeeded */
 	err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
 						  val);
-	if (err)
+	if (!err)
 		return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
 						       pullup, val);
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 10d07daf277..7faf6784442 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -946,6 +946,8 @@ config MSM_SERIAL
 
 config MSM_GENI_SERIAL
 	bool "Qualcomm on-chip GENI UART"
+	select MISC
+	imply QCOM_GENI_SE
 	help
 	  Support UART based on Generic Interface (GENI) Serial Engine (SE),
 	  used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3943ca43e49..78fd9389c03 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -11,15 +11,10 @@
 #include <clk.h>
 #include <common.h>
 #include <dm.h>
-#include <dm/pinctrl.h>
 #include <errno.h>
-#include <linux/compiler.h>
-#include <log.h>
 #include <linux/delay.h>
-#include <malloc.h>
+#include <misc.h>
 #include <serial.h>
-#include <watchdog.h>
-#include <linux/bug.h>
 
 #define UART_OVERSAMPLING	32
 #define STALE_TIMEOUT	160
@@ -116,6 +111,10 @@
 #define TX_FIFO_DEPTH_MSK	(GENMASK(21, 16))
 #define TX_FIFO_DEPTH_SHFT	16
 
+/* GENI SE QUP Registers */
+#define QUP_HW_VER_REG		0x4
+#define  QUP_SE_VERSION_2_5	0x20050000
+
 /*
  * Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
  * for uart mode.
@@ -133,11 +132,12 @@ DECLARE_GLOBAL_DATA_PTR;
 struct msm_serial_data {
 	phys_addr_t base;
 	u32 baud;
+	u32 oversampling;
 };
 
 unsigned long root_freq[] = {7372800,  14745600, 19200000, 29491200,
-					 32000000, 48000000, 64000000, 80000000,
-					 96000000, 100000000};
+			     32000000, 48000000, 64000000, 80000000,
+			     96000000, 100000000};
 
 /**
  * get_clk_cfg() - Get clock rate to apply on clock supplier.
@@ -166,8 +166,7 @@ static int get_clk_cfg(unsigned long clk_freq)
  *
  * Return: frequency, supported by clock supplier, multiple of clk_freq.
  */
-static int get_clk_div_rate(u32 baud,
-							u64 sampling_rate, u32 *clk_div)
+static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
 {
 	unsigned long ser_clk;
 	unsigned long desired_clk;
@@ -189,7 +188,7 @@ static int geni_serial_set_clock_rate(struct udevice *dev, u64 rate)
 	struct clk *clk;
 	int ret;
 
-	clk = devm_clk_get(dev, "se-clk");
+	clk = devm_clk_get(dev, NULL);
 	if (!clk)
 		return -EINVAL;
 
@@ -234,7 +233,7 @@ static inline u32 geni_se_get_tx_fifo_width(long base)
 }
 
 static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
-									int baud)
+				    int baud)
 {
 	u32 s_clk_cfg = 0;
 
@@ -245,15 +244,15 @@ static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
 	writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
 }
 
-int msm_serial_setbrg(struct udevice *dev, int baud)
+static int msm_serial_setbrg(struct udevice *dev, int baud)
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
+	u64 clk_rate;
+	u32 clk_div;
 
 	priv->baud = baud;
-	u32 clk_div;
-	u64 clk_rate;
 
-	clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, &clk_div);
+	clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
 	geni_serial_set_clock_rate(dev, clk_rate);
 	geni_serial_baud(priv->base, clk_div, baud);
 
@@ -274,7 +273,7 @@ int msm_serial_setbrg(struct udevice *dev, int baud)
  * reached.
  */
 static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
-					  int field, bool set)
+				      int field, bool set)
 {
 	u32 reg;
 	struct msm_serial_data *priv = dev_get_priv(dev);
@@ -487,6 +486,31 @@ static const struct dm_serial_ops msm_serial_ops = {
 	.setbrg = msm_serial_setbrg,
 };
 
+static void geni_set_oversampling(struct udevice *dev)
+{
+	struct msm_serial_data *priv = dev_get_priv(dev);
+	struct udevice *parent_dev = dev_get_parent(dev);
+	u32 geni_se_version;
+	int ret;
+
+	priv->oversampling = UART_OVERSAMPLING;
+
+	/*
+	 * It could happen that GENI SE IP is missing in the board's device
+	 * tree or GENI UART node is a direct child of SoC device tree node.
+	 */
+	if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
+		return;
+
+	ret = misc_read(parent_dev, QUP_HW_VER_REG,
+			&geni_se_version, sizeof(geni_se_version));
+	if (ret != sizeof(geni_se_version))
+		return;
+
+	if (geni_se_version >= QUP_SE_VERSION_2_5)
+		priv->oversampling /= 2;
+}
+
 static inline void geni_serial_init(struct udevice *dev)
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
@@ -530,6 +554,8 @@ static int msm_serial_probe(struct udevice *dev)
 {
 	struct msm_serial_data *priv = dev_get_priv(dev);
 
+	geni_set_oversampling(dev);
+
 	/* No need to reinitialize the UART after relocation */
 	if (gd->flags & GD_FLG_RELOC)
 		return 0;
@@ -554,7 +580,9 @@ static int msm_serial_ofdata_to_platdata(struct udevice *dev)
 }
 
 static const struct udevice_id msm_serial_ids[] = {
-	{.compatible = "qcom,msm-geni-uart"}, {}};
+	{ .compatible = "qcom,geni-debug-uart" },
+	{ }
+};
 
 U_BOOT_DRIVER(serial_msm_geni) = {
 	.name = "serial_msm_geni",
@@ -564,6 +592,7 @@ U_BOOT_DRIVER(serial_msm_geni) = {
 	.priv_auto = sizeof(struct msm_serial_data),
 	.probe = msm_serial_probe,
 	.ops = &msm_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
 
 #ifdef CONFIG_DEBUG_UART_MSM_GENI