Merge tag 'u-boot-rockchip-20240507' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/20628

- migrate to use OF_UPSTREAM for rv1108, rk3308, rk3328, rk356x, rk3588;

3 files changed, 118 insertions, 79 deletions

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 87075ec7134..314b903eaa0 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
 	case PCLK_HDMIPHY:
 		rate = rk3328_hdmiphy_get_clk(priv->cru);
 		break;
+	case SCLK_USB3OTG_REF:
+		rate = OSC_HZ;
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 	case PCLK_DDR:
 	case ACLK_GMAC:
 	case PCLK_GMAC:
+	case SCLK_USB3OTG_REF:
 	case SCLK_USB3OTG_SUSPEND:
 	case USB480M:
 		return 0;
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 80f65a237e8..67b2c05ec9e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -926,6 +926,26 @@ static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
 	return rk3399_saradc_get_clk(cru);
 }
 
+static ulong rk3399_pciephy_get_clk(struct rockchip_cru *cru)
+{
+	if (readl(&cru->clksel_con[18]) & BIT(10))
+		return 100 * MHz;
+	else
+		return OSC_HZ;
+}
+
+static ulong rk3399_pciephy_set_clk(struct rockchip_cru *cru, uint hz)
+{
+	if (hz == 100 * MHz)
+		rk_setreg(&cru->clksel_con[18], BIT(10));
+	else if (hz == OSC_HZ)
+		rk_clrreg(&cru->clksel_con[18], BIT(10));
+	else
+		return -EINVAL;
+
+	return rk3399_pciephy_get_clk(cru);
+}
+
 static ulong rk3399_clk_get_rate(struct clk *clk)
 {
 	struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
@@ -956,7 +976,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 	case SCLK_UART1:
 	case SCLK_UART2:
 	case SCLK_UART3:
-		return 24000000;
+	case SCLK_USB3OTG0_REF:
+	case SCLK_USB3OTG1_REF:
+		return OSC_HZ;
 	case PCLK_HDMI_CTRL:
 		break;
 	case DCLK_VOP0:
@@ -967,10 +989,14 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 	case SCLK_SARADC:
 		rate = rk3399_saradc_get_clk(priv->cru);
 		break;
+	case SCLK_PCIEPHY_REF:
+		rate = rk3399_pciephy_get_clk(priv->cru);
+		break;
 	case ACLK_VIO:
 	case ACLK_HDCP:
 	case ACLK_GIC_PRE:
 	case PCLK_DDR:
+	case ACLK_VDU:
 		break;
 	case PCLK_ALIVE:
 	case PCLK_WDT:
@@ -1049,7 +1075,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 		 * return 0 to satisfy clk_set_defaults during device probe.
 		 */
 		return 0;
-	case SCLK_DDRCLK:
+	case SCLK_DDRC:
 		ret = rk3399_ddr_set_clk(priv->cru, rate);
 		break;
 	case PCLK_EFUSE1024NS:
@@ -1057,10 +1083,14 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_SARADC:
 		ret = rk3399_saradc_set_clk(priv->cru, rate);
 		break;
+	case SCLK_PCIEPHY_REF:
+		ret = rk3399_pciephy_set_clk(priv->cru, rate);
+		break;
 	case ACLK_VIO:
 	case ACLK_HDCP:
 	case ACLK_GIC_PRE:
 	case PCLK_DDR:
+	case ACLK_VDU:
 		return 0;
 	default:
 		log_debug("Unknown clock %lu\n", clk->id);
@@ -1106,12 +1136,39 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
 	return -EINVAL;
 }
 
+static int __maybe_unused rk3399_pciephy_set_parent(struct clk *clk,
+						    struct clk *parent)
+{
+	struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
+	const char *clock_output_name;
+	int ret;
+
+	if (parent->dev == clk->dev && parent->id == SCLK_PCIEPHY_REF100M) {
+		rk_setreg(&priv->cru->clksel_con[18], BIT(10));
+		return 0;
+	}
+
+	ret = dev_read_string_index(parent->dev, "clock-output-names",
+				    parent->id, &clock_output_name);
+	if (ret < 0)
+		return -ENODATA;
+
+	if (!strcmp(clock_output_name, "xin24m")) {
+		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
 static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
 						struct clk *parent)
 {
 	switch (clk->id) {
 	case SCLK_RMII_SRC:
 		return rk3399_gmac_set_parent(clk, parent);
+	case SCLK_PCIEPHY_REF:
+		return rk3399_pciephy_set_parent(clk, parent);
 	}
 
 	debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1202,7 +1259,8 @@ static int rk3399_clk_enable(struct clk *clk)
 		rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
 		break;
 	case SCLK_PCIEPHY_REF:
-		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+			rk_clrreg(&priv->cru->clkgate_con[12], BIT(6));
 		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
@@ -1296,7 +1354,8 @@ static int rk3399_clk_disable(struct clk *clk)
 		rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
 		break;
 	case SCLK_PCIEPHY_REF:
-		rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
+		if (readl(&priv->cru->clksel_con[18]) & BIT(10))
+			rk_setreg(&priv->cru->clkgate_con[12], BIT(6));
 		break;
 	default:
 		debug("%s: unsupported clk %ld\n", __func__, clk->id);
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index baf92529348..18e76402799 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -21,7 +21,7 @@
 #include <reset.h>
 #include <syscon.h>
 #include <asm/arch-rockchip/clock.h>
-
+#include <dt-bindings/phy/phy.h>
 #include <linux/usb/phy-rockchip-usbdp.h>
 
 #define BIT_WRITEABLE_SHIFT	16
@@ -74,6 +74,8 @@ struct udphy_grf_cfg {
 struct rockchip_udphy;
 
 struct rockchip_udphy_cfg {
+	unsigned int num_phys;
+	unsigned int phy_ids[2];
 	/* resets to be requested */
 	const char * const *rst_list;
 	int num_rsts;
@@ -583,10 +585,21 @@ static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
 	return 0;
 }
 
+static int rockchip_u3phy_of_xlate(struct phy *phy,
+				   struct ofnode_phandle_args *args)
+{
+	if (args->args_count == 0)
+		return -EINVAL;
+
+	if (args->args[0] != PHY_TYPE_USB3)
+		return -EINVAL;
+
+	return 0;
+}
+
 static int rockchip_u3phy_init(struct phy *phy)
 {
-	struct udevice *parent = phy->dev->parent;
-	struct rockchip_udphy *udphy = dev_get_priv(parent);
+	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
 
 	/* DP only or high-speed, disable U3 port */
 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
@@ -599,8 +612,7 @@ static int rockchip_u3phy_init(struct phy *phy)
 
 static int rockchip_u3phy_exit(struct phy *phy)
 {
-	struct udevice *parent = phy->dev->parent;
-	struct rockchip_udphy *udphy = dev_get_priv(parent);
+	struct rockchip_udphy *udphy = dev_get_priv(phy->dev);
 
 	/* DP only or high-speed */
 	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
@@ -610,47 +622,32 @@ static int rockchip_u3phy_exit(struct phy *phy)
 }
 
 static const struct phy_ops rockchip_u3phy_ops = {
+	.of_xlate	= rockchip_u3phy_of_xlate,
 	.init		= rockchip_u3phy_init,
 	.exit		= rockchip_u3phy_exit,
 };
 
-int rockchip_u3phy_uboot_init(void)
-{
-	struct udevice *udev;
-	struct rockchip_udphy *udphy;
-	int ret;
-
-	ret = uclass_get_device_by_driver(UCLASS_PHY,
-					  DM_DRIVER_GET(rockchip_udphy_u3_port),
-					  &udev);
-	if (ret) {
-		pr_err("%s: get u3-port failed: %d\n", __func__, ret);
-		return ret;
-	}
-
-	/* DP only or high-speed, disable U3 port */
-	udphy = dev_get_priv(udev->parent);
-	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
-		udphy_u3_port_disable(udphy, true);
-		return 0;
-	}
-
-	return udphy_power_on(udphy, UDPHY_MODE_USB);
-}
-
 static int rockchip_udphy_probe(struct udevice *dev)
 {
-	const struct device_node *np = ofnode_to_np(dev_ofnode(dev));
 	struct rockchip_udphy *udphy = dev_get_priv(dev);
 	const struct rockchip_udphy_cfg *phy_cfgs;
+	unsigned int reg;
 	int id, ret;
 
 	udphy->dev = dev;
 
-	id = of_alias_get_id(np, "usbdp");
-	if (id < 0)
-		id = 0;
-	udphy->id = id;
+	ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 0, &reg);
+	if (ret) {
+		dev_err(dev, "failed to read reg[0] property\n");
+		return ret;
+	}
+	if (reg == 0 && dev_read_addr_cells(dev) == 2) {
+		ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", 1, &reg);
+		if (ret) {
+			dev_err(dev, "failed to read reg[1] property\n");
+			return ret;
+		}
+	}
 
 	phy_cfgs = (const struct rockchip_udphy_cfg *)dev_get_driver_data(dev);
 	if (!phy_cfgs) {
@@ -659,6 +656,20 @@ static int rockchip_udphy_probe(struct udevice *dev)
 	}
 	udphy->cfgs = phy_cfgs;
 
+	/* find the phy-id from the io address */
+	udphy->id = -ENODEV;
+	for (id = 0; id < udphy->cfgs->num_phys; id++) {
+		if (reg == udphy->cfgs->phy_ids[id]) {
+			udphy->id = id;
+			break;
+		}
+	}
+
+	if (udphy->id < 0) {
+		dev_err(dev, "no matching device found\n");
+		return -ENODEV;
+	}
+
 	ret = regmap_init_mem(dev_ofnode(dev), &udphy->pma_regmap);
 	if (ret)
 		return ret;
@@ -671,40 +682,6 @@ static int rockchip_udphy_probe(struct udevice *dev)
 	return 0;
 }
 
-static int rockchip_udphy_bind(struct udevice *parent)
-{
-	struct udevice *child;
-	ofnode subnode;
-	const char *node_name;
-	int ret;
-
-	dev_for_each_subnode(subnode, parent) {
-		if (!ofnode_valid(subnode)) {
-			printf("%s: no subnode for %s", __func__, parent->name);
-			return -ENXIO;
-		}
-
-		node_name = ofnode_get_name(subnode);
-		debug("%s: subnode %s\n", __func__, node_name);
-
-		/* if there is no match, continue */
-		if (strcasecmp(node_name, "usb3-port"))
-			continue;
-
-		/* node name is usb3-port */
-		ret = device_bind_driver_to_node(parent,
-						 "rockchip_udphy_u3_port",
-						 node_name, subnode, &child);
-		if (ret) {
-			printf("%s: '%s' cannot bind its driver\n",
-			       __func__, node_name);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
 static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
 {
 	/* configure phy reference clock */
@@ -838,6 +815,11 @@ static const char * const rk3588_udphy_rst_l[] = {
 };
 
 static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
+	.num_phys = 2,
+	.phy_ids = {
+		0xfed80000,
+		0xfed90000,
+	},
 	.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
 	.rst_list = rk3588_udphy_rst_l,
 	.grfcfg	= {
@@ -864,17 +846,11 @@ static const struct udevice_id rockchip_udphy_dt_match[] = {
 	{ /* sentinel */ }
 };
 
-U_BOOT_DRIVER(rockchip_udphy_u3_port) = {
-	.name		= "rockchip_udphy_u3_port",
-	.id		= UCLASS_PHY,
-	.ops		= &rockchip_u3phy_ops,
-};
-
 U_BOOT_DRIVER(rockchip_udphy) = {
 	.name		= "rockchip_udphy",
 	.id		= UCLASS_PHY,
 	.of_match	= rockchip_udphy_dt_match,
 	.probe		= rockchip_udphy_probe,
-	.bind		= rockchip_udphy_bind,
+	.ops		= &rockchip_u3phy_ops,
 	.priv_auto	= sizeof(struct rockchip_udphy),
 };