diff options
| author | Tom Rini <trini@konsulko.com> | 2020-09-24 08:34:54 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-24 08:34:54 -0400 |
| commit | 1da91d9bcd6e5ef046c1df0d373d0df87b1e8a72 (patch) | |
| tree | f758747a6925be502650c1a310e54758bdccdc41 /drivers | |
| parent | 55004fa43364e9824b8231e2060f9d7af9c7570a (diff) | |
| parent | 5f50b88ab60a9d2ef2a68a7fc889e78520691e40 (diff) | |
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Enable NET_RANDOM_ETHADDR on Espressobin (Acked-by Kosta)
- Espressobin & Clearfog: fdtfile enhancements
- A37xx PCI: Disable link training when unloading driver
- A37xx: increase CONFIG_SYS_BOOTM_LEN to 64MB
- Add Macronix mx25u12835f support, used on uDPU and ESPRESSObin v7
- dns325: Correct CONFIG_NR_DRAM_BANKS parameter
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 1 | ||||
| -rw-r--r-- | drivers/pci/pci-aardvark.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 114ebacde1c..bc9d4f7e9f8 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -151,6 +151,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, + { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index b2c417701f2..babb84ca937 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -647,10 +647,15 @@ static int pcie_advk_probe(struct udevice *dev) static int pcie_advk_remove(struct udevice *dev) { struct pcie_advk *pcie = dev_get_priv(dev); + u32 reg; if (dm_gpio_is_valid(&pcie->reset_gpio)) dm_gpio_set_value(&pcie->reset_gpio, 1); + reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); + reg &= ~LINK_TRAINING_EN; + advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); + return 0; } |