diff options
| author | Tom Rini <trini@konsulko.com> | 2024-09-16 16:43:53 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-09-16 16:43:53 -0600 |
| commit | 773f138632b95ea6b0c4a7a2b653174c19749da5 (patch) | |
| tree | be5ff0fbccb414a692f4fd02ba1da651e4500c6c /drivers | |
| parent | fca70d61817b9ad2fb4b4821b029e55f1945997b (diff) | |
| parent | 3aa2eac4f06de8ca5871543f21b88d568f33effc (diff) | |
Merge patch series "Arm: npcm: modify npcm8xx boot setting"
Jim Liu <jim.t90615@gmail.com> says:
Modify npcm8xx new boot design.
Correct memory setting and set gpio default value.
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index ff49819b58d..67e564f85c3 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -48,6 +48,7 @@ #define GPIO_OES 0x70 /* Output Enable Set */ #define GPIO_OEC 0x74 /* Output Enable Clear */ +#define NPCM8XX_NUM_GPIO_BANK 8 #define NPCM8XX_GPIO_PER_BANK 32 #define GPIOX_OFFSET 16 @@ -967,6 +968,18 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector, } #endif +static void npcm8xx_pinctrl_clear_events(struct npcm8xx_pinctrl_priv *priv) +{ + void __iomem *base; + int i; + + for (i = 0; i < NPCM8XX_NUM_GPIO_BANK; i++) { + base = priv->gpio_base + (0x1000 * i); + clrbits_le32(base + GPIO_EVEN, 0xFFFFFFFF); + setbits_le32(base + GPIO_EVST, 0xFFFFFFFF); + } +} + static struct pinctrl_ops npcm8xx_pinctrl_ops = { .set_state = pinctrl_generic_set_state, .get_pins_count = npcm8xx_get_pins_count, @@ -1001,6 +1014,11 @@ static int npcm8xx_pinctrl_probe(struct udevice *dev) if (IS_ERR(priv->rst_regmap)) return -EINVAL; + /* + * Clear all previous gpio events, otherwise it may produce + * unexpected interrupts during kernel booting. + */ + npcm8xx_pinctrl_clear_events(priv); return 0; } |