diff options
| author | Michal Simek <michal.simek@amd.com> | 2024-05-29 16:48:01 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-06-17 16:02:29 +0200 |
| commit | 9bf522cd5c521f9304e7d54f0cf97eb6c08a0696 (patch) | |
| tree | be21f1be062bcdab9d1bc9c31bc846177b4c08cc /drivers | |
| parent | 4950a98d14da12335c960c81a62754b667c11300 (diff) | |
spi: versal2: Enable spi drivers for Versal Gen 2
Enable and update OSPI/QSPI/GQSPI drivers to support Versal Gen 2 SoCs.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/691782470f56f7d49a3204f6757296f2752d4156.1716994063.git.michal.simek@amd.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/spi/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 3 | ||||
| -rw-r--r-- | drivers/spi/zynqmp_gqspi.c | 6 |
3 files changed, 7 insertions, 4 deletions
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 35030ab3556..cd785aefd56 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -156,7 +156,7 @@ config CQSPI_REF_CLK config CADENCE_OSPI_VERSAL bool "Configure Versal OSPI" - depends on (ARCH_VERSAL || ARCH_VERSAL_NET) && CADENCE_QSPI + depends on (ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2) && CADENCE_QSPI imply DM_GPIO help This option is used to enable Versal OSPI DMA operations which diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 75e52232010..9c466f8695e 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -253,7 +253,8 @@ static int cadence_spi_probe(struct udevice *bus) /* Versal and Versal-NET use spi calibration to set read delay */ if (CONFIG_IS_ENABLED(ARCH_VERSAL) || - CONFIG_IS_ENABLED(ARCH_VERSAL_NET)) + CONFIG_IS_ENABLED(ARCH_VERSAL_NET) || + CONFIG_IS_ENABLED(ARCH_VERSAL2)) if (priv->read_delay >= 0) priv->read_delay = -1; diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c index 61349a4da53..ae795e50b0a 100644 --- a/drivers/spi/zynqmp_gqspi.c +++ b/drivers/spi/zynqmp_gqspi.c @@ -106,7 +106,8 @@ #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT 2 #define GQSPI_DATA_DLY_ADJ_OFST 0x000001F8 #define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \ - IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \ + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || \ + IS_ENABLED(CONFIG_ARCH_VERSAL2)) ? \ 0xFF180390 : 0xF103003C #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK 0x00000020 #define GQSPI_FREQ_37_5MHZ 37500000 @@ -316,7 +317,8 @@ static void zynqmp_qspi_set_tapdelay(struct udevice *bus, u32 baudrateval) __func__, clk_rate, baudrateval, reqhz); if (!(IS_ENABLED(CONFIG_ARCH_VERSAL) || - IS_ENABLED(CONFIG_ARCH_VERSAL_NET))) { + IS_ENABLED(CONFIG_ARCH_VERSAL_NET) || + IS_ENABLED(CONFIG_ARCH_VERSAL2))) { if (reqhz <= GQSPI_FREQ_40MHZ) { tapdlybypass = TAP_DLY_BYPASS_LQSPI_RX_VALUE << TAP_DLY_BYPASS_LQSPI_RX_SHIFT; |