Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra

18 files changed, 1450 insertions, 0 deletions

diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c
index b83df351e74..3d1e18854f2 100644
--- a/drivers/gpio/tegra_gpio.c
+++ b/drivers/gpio/tegra_gpio.c
@@ -248,6 +248,16 @@ static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
 	return 0;
 }
 
+static int tegra_gpio_rfree(struct udevice *dev, unsigned int offset)
+{
+	struct tegra_port_info *state = dev_get_priv(dev);
+
+	/* Set the pin as a SFIO */
+	set_config(state->base_gpio + offset, CFG_SFIO);
+
+	return 0;
+}
+
 static const struct dm_gpio_ops gpio_tegra_ops = {
 	.direction_input	= tegra_gpio_direction_input,
 	.direction_output	= tegra_gpio_direction_output,
@@ -255,6 +265,7 @@ static const struct dm_gpio_ops gpio_tegra_ops = {
 	.set_value		= tegra_gpio_set_value,
 	.get_function		= tegra_gpio_get_function,
 	.xlate			= tegra_gpio_xlate,
+	.rfree			= tegra_gpio_rfree,
 };
 
 /*
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 5a61cd45b8c..ec7ccc3a63f 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -184,6 +184,15 @@ config SPL_DM_PMIC_PFUZE100
 	This config enables implementation of driver-model pmic uclass features
 	for PMIC PFUZE100 in SPL. The driver implements read/write operations.
 
+config DM_PMIC_MAX8907
+	bool "Enable Driver Model for PMIC MAX8907"
+	---help---
+	This config enables implementation of driver-model pmic uclass features
+	for PMIC MAX8907. The driver implements read/write operations.
+	This is a Power Management IC with a decent set of peripherals from which
+	3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators,
+	Real-Time Clock (RTC) and more with I2C Compatible Interface.
+
 config DM_PMIC_MAX77663
 	bool "Enable Driver Model for PMIC MAX77663"
 	---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 2210b1a64ae..6bebffb05a6 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_$(PHASE_)DM_PMIC) += pmic-uclass.o
 obj-$(CONFIG_$(PHASE_)DM_PMIC_FAN53555) += fan53555.o
 obj-$(CONFIG_$(PHASE_)DM_PMIC_DA9063) += da9063.o
 obj-$(CONFIG_$(PHASE_)DM_PMIC_MAX77663) += max77663.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_MAX8907) += max8907.o
 obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
 obj-$(CONFIG_DM_PMIC_MAX8998) += max8998.o
 obj-$(CONFIG_DM_PMIC_MC34708) += mc34708.o
diff --git a/drivers/power/pmic/max8907.c b/drivers/power/pmic/max8907.c
new file mode 100644
index 00000000000..a7ef70177de
--- /dev/null
+++ b/drivers/power/pmic/max8907.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright(C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/lists.h>
+#include <power/pmic.h>
+#include <power/max8907.h>
+
+static const struct pmic_child_info pmic_children_info[] = {
+	{ .prefix = "ldo", .driver = MAX8907_LDO_DRIVER },
+	{ .prefix = "sd", .driver = MAX8907_SD_DRIVER },
+	{ },
+};
+
+static int max8907_write(struct udevice *dev, uint reg, const uint8_t *buff, int len)
+{
+	int ret;
+
+	ret = dm_i2c_write(dev, reg, buff, len);
+	if (ret) {
+		log_debug("%s: write error to device: %p register: %#x!\n",
+			  __func__, dev, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int max8907_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+	int ret;
+
+	ret = dm_i2c_read(dev, reg, buff, len);
+	if (ret) {
+		log_debug("%s: read error from device: %p register: %#x!\n",
+			  __func__, dev, reg);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int max8907_bind(struct udevice *dev)
+{
+	ofnode regulators_node;
+	int children, ret;
+
+	if (IS_ENABLED(CONFIG_SYSRESET_MAX8907) &&
+	    dev_read_bool(dev, "maxim,system-power-controller")) {
+		ret = device_bind_driver_to_node(dev, MAX8907_RST_DRIVER,
+						 "sysreset", dev_ofnode(dev),
+						 NULL);
+		if (ret) {
+			log_debug("%s: cannot bind SYSRESET (ret = %d)\n",
+				  __func__, ret);
+			return ret;
+		}
+	}
+
+	regulators_node = dev_read_subnode(dev, "regulators");
+	if (!ofnode_valid(regulators_node)) {
+		log_err("%s regulators subnode not found!\n", dev->name);
+		return -ENXIO;
+	}
+
+	log_debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+	children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+	if (!children)
+		log_err("%s - no child found\n", dev->name);
+
+	/* Always return success for this device */
+	return 0;
+}
+
+static struct dm_pmic_ops max8907_ops = {
+	.read = max8907_read,
+	.write = max8907_write,
+};
+
+static const struct udevice_id max8907_ids[] = {
+	{ .compatible = "maxim,max8907" },
+	{ }
+};
+
+U_BOOT_DRIVER(pmic_max8907) = {
+	.name = "max8907_pmic",
+	.id = UCLASS_PMIC,
+	.of_match = max8907_ids,
+	.bind = max8907_bind,
+	.ops = &max8907_ops,
+};
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 95912ef5633..7ed435f0202 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -148,6 +148,15 @@ config SPL_REGULATOR_PWM
 	  This config enables implementation of driver-model regulator uclass
 	  features for PWM regulators in SPL.
 
+config DM_REGULATOR_MAX8907
+	bool "Enable Driver Model for REGULATOR MAX8907"
+	depends on DM_REGULATOR && DM_PMIC_MAX8907
+	---help---
+	This config enables implementation of driver-model regulator uclass
+	features for REGULATOR MAX8907. The driver supports both DC-to-DC
+	Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators
+	found in MAX8907 PMIC and implements get/set api for value and enable.
+
 config DM_REGULATOR_MAX77663
 	bool "Enable Driver Model for REGULATOR MAX77663"
 	depends on DM_REGULATOR && DM_PMIC_MAX77663
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 0ee5d908a2a..ee8f56ea3b9 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_DRIVEVBUS) += axp_drivevbus.o
 obj-$(CONFIG_$(PHASE_)REGULATOR_AXP_USB_POWER) += axp_usb_power.o
 obj-$(CONFIG_$(PHASE_)DM_REGULATOR_DA9063) += da9063.o
 obj-$(CONFIG_$(PHASE_)DM_REGULATOR_MAX77663) += max77663_regulator.o
+obj-$(CONFIG_$(PHASE_)DM_REGULATOR_MAX8907) += max8907_regulator.o
 obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
 obj-$(CONFIG_DM_REGULATOR_NPCM8XX) += npcm8xx_regulator.o
 obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100) += pfuze100.o
diff --git a/drivers/power/regulator/max8907_regulator.c b/drivers/power/regulator/max8907_regulator.c
new file mode 100644
index 00000000000..00ecd4b808b
--- /dev/null
+++ b/drivers/power/regulator/max8907_regulator.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright(C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <power/pmic.h>
+#include <power/regulator.h>
+#include <power/max8907.h>
+
+static const char max8907_regmap[] = {
+	0x00, MAX8907_REG_SDCTL1, MAX8907_REG_SDCTL2, MAX8907_REG_SDCTL3,
+	 MAX8907_REG_LDOCTL1,  MAX8907_REG_LDOCTL2,  MAX8907_REG_LDOCTL3,
+	 MAX8907_REG_LDOCTL4,  MAX8907_REG_LDOCTL5,  MAX8907_REG_LDOCTL6,
+	 MAX8907_REG_LDOCTL7,  MAX8907_REG_LDOCTL8,  MAX8907_REG_LDOCTL9,
+	MAX8907_REG_LDOCTL10, MAX8907_REG_LDOCTL11, MAX8907_REG_LDOCTL12,
+	MAX8907_REG_LDOCTL13, MAX8907_REG_LDOCTL14, MAX8907_REG_LDOCTL15,
+	MAX8907_REG_LDOCTL16, MAX8907_REG_LDOCTL17, MAX8907_REG_LDOCTL18,
+	MAX8907_REG_LDOCTL19, MAX8907_REG_LDOCTL20
+};
+
+static int max8907_enable(struct udevice *dev, int op, bool *enable)
+{
+	struct dm_regulator_uclass_plat *uc_pdata =
+					dev_get_uclass_plat(dev);
+	int val, ret = 0;
+
+	if (op == PMIC_OP_GET) {
+		val = pmic_reg_read(dev->parent, uc_pdata->ctrl_reg);
+		if (val < 0)
+			return val;
+
+		if (val & MAX8907_MASK_LDO_EN)
+			*enable = true;
+		else
+			*enable = false;
+	} else if (op == PMIC_OP_SET) {
+		if (*enable) {
+			ret = pmic_clrsetbits(dev->parent,
+					      uc_pdata->ctrl_reg,
+					      MAX8907_MASK_LDO_EN |
+					      MAX8907_MASK_LDO_SEQ,
+					      MAX8907_MASK_LDO_EN |
+					      MAX8907_MASK_LDO_SEQ);
+		} else {
+			ret = pmic_clrsetbits(dev->parent,
+					      uc_pdata->ctrl_reg,
+					      MAX8907_MASK_LDO_EN |
+					      MAX8907_MASK_LDO_SEQ,
+					      MAX8907_MASK_LDO_SEQ);
+		}
+	}
+
+	return ret;
+}
+
+static int max8907_get_enable(struct udevice *dev)
+{
+	bool enable = false;
+	int ret;
+
+	ret = max8907_enable(dev, PMIC_OP_GET, &enable);
+	if (ret)
+		return ret;
+
+	return enable;
+}
+
+static int max8907_set_enable(struct udevice *dev, bool enable)
+{
+	return max8907_enable(dev, PMIC_OP_SET, &enable);
+}
+
+/**
+ * max8907_volt2hex() - convert voltage in uV into
+ *			applicable to register hex value
+ *
+ * @idx:	regulator index
+ * @uV:		voltage in uV
+ *
+ * Return: voltage in hex on success, -ve on failure
+ */
+static int max8907_volt2hex(int idx, int uV)
+{
+	switch (idx) {
+	case 1: /* SD1 */
+		if (uV > SD1_VOLT_MAX || uV < SD1_VOLT_MIN)
+			break;
+
+		return (uV - SD1_VOLT_MIN) / SD1_VOLT_STEP;
+
+	case 2: /* SD2 */
+		if (uV > SD2_VOLT_MAX || uV < SD2_VOLT_MIN)
+			break;
+
+		return (uV - SD2_VOLT_MIN) / SD2_VOLT_STEP;
+
+	case 3: /* SD3 */
+		if (uV > SD2_VOLT_MAX || uV < SD2_VOLT_MIN)
+			break;
+
+		return (uV - SD2_VOLT_MIN) / SD2_VOLT_STEP;
+
+	case 5: /* LDO2 */
+	case 6: /* LDO3 */
+	case 20: /* LDO17 */
+	case 21: /* LDO18 */
+		if (uV > LDO_650_VOLT_MAX || uV < LDO_650_VOLT_MIN)
+			break;
+
+		return (uV - LDO_650_VOLT_MIN) / LDO_650_VOLT_STEP;
+
+	default: /* LDO1, 4..16, 19..20 */
+		if (uV > LDO_750_VOLT_MAX || uV < LDO_750_VOLT_MIN)
+			break;
+
+		return (uV - LDO_750_VOLT_MIN) / LDO_750_VOLT_STEP;
+	};
+
+	return -EINVAL;
+}
+
+/**
+ * max8907_hex2volt() - convert register hex value into
+ *			actual voltage in uV
+ *
+ * @idx:	regulator index
+ * @hex:	hex value of register
+ *
+ * Return: voltage in uV on success, -ve on failure
+ */
+static int max8907_hex2volt(int idx, int hex)
+{
+	switch (idx) {
+	case 1:
+		return hex * SD1_VOLT_STEP + SD1_VOLT_MIN;
+
+	case 2:
+		return hex * SD2_VOLT_STEP + SD2_VOLT_MIN;
+
+	case 3:
+		return hex * SD3_VOLT_STEP + SD3_VOLT_MIN;
+
+	case 5: /* LDO2 */
+	case 6: /* LDO3 */
+	case 20: /* LDO17 */
+	case 21: /* LDO18 */
+		return hex * LDO_650_VOLT_STEP + LDO_650_VOLT_MIN;
+
+	default: /* LDO1, 4..16, 19..20 */
+		return hex * LDO_750_VOLT_STEP + LDO_750_VOLT_MIN;
+	};
+
+	return -EINVAL;
+}
+
+static int max8907_val(struct udevice *dev, int op, int *uV)
+{
+	struct dm_regulator_uclass_plat *uc_pdata =
+					dev_get_uclass_plat(dev);
+	int idx = dev->driver_data;
+	int hex, ret;
+
+	if (op == PMIC_OP_GET) {
+		hex = pmic_reg_read(dev->parent, uc_pdata->volt_reg);
+		if (hex < 0)
+			return hex;
+
+		*uV = 0;
+
+		ret = max8907_hex2volt(idx, hex);
+		if (ret < 0)
+			return ret;
+		*uV = ret;
+
+		return 0;
+	}
+
+	hex = max8907_volt2hex(idx, *uV);
+	if (hex < 0)
+		return hex;
+
+	return pmic_reg_write(dev->parent, uc_pdata->volt_reg, hex);
+}
+
+static int max8907_get_value(struct udevice *dev)
+{
+	int uV;
+	int ret;
+
+	ret = max8907_val(dev, PMIC_OP_GET, &uV);
+	if (ret)
+		return ret;
+
+	return uV;
+}
+
+static int max8907_set_value(struct udevice *dev, int uV)
+{
+	return max8907_val(dev, PMIC_OP_SET, &uV);
+}
+
+static const struct dm_regulator_ops max8907_regulator_ops = {
+	.get_value  = max8907_get_value,
+	.set_value  = max8907_set_value,
+	.get_enable = max8907_get_enable,
+	.set_enable = max8907_set_enable,
+};
+
+static int max8907_sd_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_plat *uc_pdata =
+					dev_get_uclass_plat(dev);
+	int idx = dev->driver_data;
+
+	uc_pdata->type = REGULATOR_TYPE_BUCK;
+	uc_pdata->ctrl_reg = max8907_regmap[idx];
+	uc_pdata->volt_reg = uc_pdata->ctrl_reg + MAX8907_VOUT;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(max8907_sd) = {
+	.name = MAX8907_SD_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &max8907_regulator_ops,
+	.probe = max8907_sd_probe,
+};
+
+static int max8907_ldo_probe(struct udevice *dev)
+{
+	struct dm_regulator_uclass_plat *uc_pdata =
+					dev_get_uclass_plat(dev);
+	/* LDO regulator id is shifted by number for SD regulators */
+	int idx = dev->driver_data + 3;
+
+	uc_pdata->type = REGULATOR_TYPE_LDO;
+	uc_pdata->ctrl_reg = max8907_regmap[idx];
+	uc_pdata->volt_reg = uc_pdata->ctrl_reg + MAX8907_VOUT;
+
+	return 0;
+}
+
+U_BOOT_DRIVER(max8907_ldo) = {
+	.name = MAX8907_LDO_DRIVER,
+	.id = UCLASS_REGULATOR,
+	.ops = &max8907_regulator_ops,
+	.probe = max8907_ldo_probe,
+};
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 4972905482a..aa83073c96a 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -131,6 +131,13 @@ config SYSRESET_MAX77663
 	help
 	  Enable system power management functions found in MAX77663 PMIC.
 
+config SYSRESET_MAX8907
+	bool "Enable support for MAX8907 PMIC System Reset"
+	depends on DM_PMIC_MAX8907
+	select SYSRESET_CMD_POWEROFF if CMD_POWEROFF
+	help
+	  Enable system power management functions found in MAX8907 PMIC.
+
 config SYSRESET_MICROBLAZE
 	bool "Enable support for Microblaze soft reset"
 	depends on MICROBLAZE
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index ded91a4d325..f5c78b25896 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SYSRESET_CV1800B) += sysreset_cv1800b.o
 obj-$(CONFIG_$(PHASE_)POWEROFF_GPIO) += poweroff_gpio.o
 obj-$(CONFIG_$(PHASE_)SYSRESET_GPIO) += sysreset_gpio.o
 obj-$(CONFIG_$(PHASE_)SYSRESET_MAX77663) += sysreset_max77663.o
+obj-$(CONFIG_$(PHASE_)SYSRESET_MAX8907) += sysreset_max8907.o
 obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
 obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
diff --git a/drivers/sysreset/sysreset_max8907.c b/drivers/sysreset/sysreset_max8907.c
new file mode 100644
index 00000000000..6f62af9bffe
--- /dev/null
+++ b/drivers/sysreset/sysreset_max8907.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Copyright(C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <i2c.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <power/pmic.h>
+#include <power/max8907.h>
+
+static int max8907_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	switch (type) {
+	case SYSRESET_POWER:
+	case SYSRESET_POWER_OFF:
+		/* MAX8907: PWR_OFF > RESET_CNFG */
+		pmic_clrsetbits(dev->parent, MAX8907_REG_RESET_CNFG,
+				MASK_POWER_OFF, MASK_POWER_OFF);
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops max8907_sysreset = {
+	.request = max8907_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_max8907) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= MAX8907_RST_DRIVER,
+	.ops	= &max8907_sysreset,
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index fe70e98f964..dfe4b3b8a02 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -581,6 +581,14 @@ config VIDEO_LCD_LG_LD070WX3
 	  Say Y here if you want to enable support for LG LD070WX3
 	  800x1280 DSI video mode panel.
 
+config VIDEO_LCD_LG_LH400WV3
+	bool "LH400WV3-SD04 DSI LCD panel support"
+	depends on PANEL && BACKLIGHT
+	select VIDEO_MIPI_DSI
+	help
+	  Say Y here if you want to enable support for LG LH400WV3
+	  480x800 DSI video mode panel.
+
 config VIDEO_LCD_RAYDIUM_RM68200
 	bool "RM68200 DSI LCD panel support"
 	select VIDEO_MIPI_DSI
@@ -668,6 +676,14 @@ config VIDEO_LCD_TDO_TL070WSH30
 	Say Y here if you want to enable support for TDO TL070WSH30
 	1024x600 DSI video mode panel.
 
+config VIDEO_LCD_HITACHI_TX10D07VM0BAA
+	tristate "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel"
+	depends on PANEL && BACKLIGHT
+	select VIDEO_MIPI_DSI
+	help
+	  Say Y here if you want to enable support for Hitachi TX10D07VM0BAA
+	  TFT-LCD module. The panel has a 480x800 resolution.
+
 config VIDEO_LCD_HITACHI_TX18D42VM
 	bool "Hitachi tx18d42vm LVDS LCD panel support"
 	---help---
@@ -767,6 +783,16 @@ config ATMEL_HLCD
 	help
 	   HLCDC supports video output to an attached LCD panel.
 
+config BACKLIGHT_AAT2870
+	bool "Backlight Driver for AAT2870"
+	depends on BACKLIGHT
+	select DM_I2C
+	help
+	  Say Y to enable the backlight driver for Skyworks AAT2870 LED
+	  Backlight Driver and Multiple LDO Lighting Management Unit.
+	  Only backlight is supported as for now. Supported backlight
+	  level range is from 2 to 255 with step of 1.
+
 config BACKLIGHT_LM3532
 	bool "Backlight Driver for LM3532"
 	depends on BACKLIGHT
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 31f68585fe4..ebe4a3961fc 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)BMP) += bmp.o
 
 endif
 
+obj-$(CONFIG_BACKLIGHT_AAT2870) += aat2870_backlight.o
 obj-$(CONFIG_BACKLIGHT_LM3532) += lm3532_backlight.o
 obj-$(CONFIG_BACKLIGHT_LM3533) += lm3533_backlight.o
 obj-$(CONFIG_BACKLIGHT_LP855x) += lp855x_backlight.o
@@ -58,8 +59,10 @@ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o
 obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o
+obj-$(CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA) += hitachi-tx10d07vm0baa.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o
+obj-$(CONFIG_VIDEO_LCD_LG_LH400WV3) += lg-lh400wv3-sd04.o
 obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o
 obj-$(CONFIG_VIDEO_LCD_NOVATEK_NT35510) += novatek-nt35510.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
diff --git a/drivers/video/aat2870_backlight.c b/drivers/video/aat2870_backlight.c
new file mode 100644
index 00000000000..209d15b3639
--- /dev/null
+++ b/drivers/video/aat2870_backlight.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_PANEL_BACKLIGHT
+
+#include <backlight.h>
+#include <dm.h>
+#include <i2c.h>
+#include <log.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <power/regulator.h>
+
+#define AAT2870_BL_MIN_BRIGHTNESS	0x01
+#define AAT2870_BL_DEF_BRIGHTNESS	0x64
+#define AAT2870_BL_MAX_BRIGHTNESS	0xff
+
+#define AAT2870_BL_CH_EN		0x00
+#define AAT2870_BLM			0x01
+
+#define AAT2870_BL_CH_ALL		0xff
+
+#define AAT2870_CURRENT_MAX		27900000
+#define AAT2870_CURRENT_STEP		900000
+
+struct aat2870_backlight_priv {
+	struct gpio_desc enable_gpio;
+
+	int channels;
+	int max_current;
+};
+
+static int aat2870_backlight_enable(struct udevice *dev)
+{
+	struct aat2870_backlight_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	dm_gpio_set_value(&priv->enable_gpio, 1);
+
+	/* Enable backlight for defined set of channels */
+	ret = dm_i2c_reg_write(dev, AAT2870_BL_CH_EN, priv->channels);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int aat2870_backlight_set_brightness(struct udevice *dev, int percent)
+{
+	struct aat2870_backlight_priv *priv = dev_get_priv(dev);
+	int brightness, ret;
+
+	if (percent == BACKLIGHT_DEFAULT)
+		percent = AAT2870_BL_DEF_BRIGHTNESS;
+
+	if (percent < AAT2870_BL_MIN_BRIGHTNESS)
+		percent = AAT2870_BL_MIN_BRIGHTNESS;
+
+	if (percent > AAT2870_BL_MAX_BRIGHTNESS)
+		percent = AAT2870_BL_MAX_BRIGHTNESS;
+
+	brightness = percent * priv->max_current;
+	brightness /= AAT2870_BL_MAX_BRIGHTNESS;
+
+	/* Set brightness level */
+	ret = dm_i2c_reg_write(dev, AAT2870_BLM, brightness);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int aat2870_backlight_of_to_plat(struct udevice *dev)
+{
+	struct aat2870_backlight_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = gpio_request_by_name(dev, "enable-gpios", 0,
+				   &priv->enable_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_err("%s: cannot get enable-gpios (%d)\n",
+			__func__, ret);
+		return ret;
+	}
+
+	/* Backlight is one of children but has no dedicated driver */
+	ofnode backlight = ofnode_find_subnode(dev_ofnode(dev), "backlight");
+	if (ofnode_valid(backlight) && ofnode_is_enabled(backlight)) {
+		/* Number of channel is equal to bit number */
+		priv->channels = dev_read_u32_default(dev, "channels", AAT2870_BL_CH_ALL);
+		if (priv->channels != AAT2870_BL_CH_ALL)
+			priv->channels = BIT(priv->channels);
+
+		/* 450mA - 27900mA range with a 900mA step */
+		priv->max_current = dev_read_u32_default(dev, "current-max-microamp",
+							 AAT2870_CURRENT_MAX);
+		priv->max_current /= AAT2870_CURRENT_STEP;
+	}
+
+	return 0;
+}
+
+static int aat2870_backlight_probe(struct udevice *dev)
+{
+	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
+		return -EPROTONOSUPPORT;
+
+	return 0;
+}
+
+static const struct backlight_ops aat2870_backlight_ops = {
+	.enable = aat2870_backlight_enable,
+	.set_brightness = aat2870_backlight_set_brightness,
+};
+
+static const struct udevice_id aat2870_backlight_ids[] = {
+	{ .compatible = "analogictech,aat2870" },
+	{ .compatible = "skyworks,aat2870" },
+	{ }
+};
+
+U_BOOT_DRIVER(aat2870_backlight) = {
+	.name		= "aat2870_backlight",
+	.id		= UCLASS_PANEL_BACKLIGHT,
+	.of_match	= aat2870_backlight_ids,
+	.of_to_plat	= aat2870_backlight_of_to_plat,
+	.probe		= aat2870_backlight_probe,
+	.ops		= &aat2870_backlight_ops,
+	.priv_auto	= sizeof(struct aat2870_backlight_priv),
+};
diff --git a/drivers/video/hitachi-tx10d07vm0baa.c b/drivers/video/hitachi-tx10d07vm0baa.c
new file mode 100644
index 00000000000..95b2f7bfc41
--- /dev/null
+++ b/drivers/video/hitachi-tx10d07vm0baa.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hitachi TX10D07VM0BAA DSI panel driver
+ *
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <asm/gpio.h>
+
+struct hitachi_tx10d07vm0baa_priv {
+	struct udevice *avci;
+	struct udevice *iovcc;
+
+	struct udevice *backlight;
+
+	struct gpio_desc reset_gpio;
+};
+
+static struct display_timing default_timing = {
+	.pixelclock.typ		= 29816000,
+	.hactive.typ		= 480,
+	.hfront_porch.typ	= 10,
+	.hback_porch.typ	= 10,
+	.hsync_len.typ		= 10,
+	.vactive.typ		= 800,
+	.vfront_porch.typ	= 4,
+	.vback_porch.typ	= 4,
+	.vsync_len.typ		= 4,
+};
+
+#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
+		static const u8 b[] = { cmd, seq };			\
+		int ret;						\
+		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+static int hitachi_tx10d07vm0baa_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	int ret;
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_PARTIAL_AREA, 0x00,
+			      0x00, 0x03, 0x1f);
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_SCROLL_AREA, 0x00,
+			      0x00, 0x03, 0x20, 0x00, 0x00);
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_ADDRESS_MODE, 0x0a);
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_SCROLL_START, 0x00,
+			      0x00);
+
+	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT);
+	if (ret) {
+		log_debug("%s: failed to set pixel format: %d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x00);
+	if (ret) {
+		log_debug("%s: failed to set tear scanline: %d\n", __func__, ret);
+		return ret;
+	}
+
+	dsi_generic_write_seq(dsi, 0x71, 0x00);		/* Ex_Vsync_en */
+
+	dsi_generic_write_seq(dsi, 0xb2, 0x00);		/* VCSEL */
+	dsi_generic_write_seq(dsi, 0xb4, 0xaa);		/* setvgmpm */
+	dsi_generic_write_seq(dsi, 0xb5, 0x33);		/* rbias1 */
+	dsi_generic_write_seq(dsi, 0xb6, 0x03);		/* rbias2 */
+
+	dsi_generic_write_seq(dsi, 0xb7, 0x1a, 0x33, 0x03, 0x03,
+			      0x03, 0x00, 0x00, 0x01, 0x02, 0x00,
+			      0x00, 0x04, 0x00, 0x01, 0x01, 0x01);	/* set_ddvdhp */
+	dsi_generic_write_seq(dsi, 0xb8, 0x1c, 0x53, 0x03, 0x03,
+			      0x00, 0x01, 0x02, 0x00, 0x00, 0x04,
+			      0x00, 0x01, 0x01);			/* set_ddvdhm */
+
+	dsi_generic_write_seq(dsi, 0xb9, 0x0a, 0x01, 0x01, 0x00,
+			      0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgh */
+	dsi_generic_write_seq(dsi, 0xba, 0x0f, 0x01, 0x01, 0x00,
+			      0x00, 0x00, 0x02, 0x00, 0x02, 0x01);	/* set_vgl */
+	dsi_generic_write_seq(dsi, 0xbb, 0x00, 0x00, 0x00, 0x00,
+			      0x01, 0x02, 0x01);			/* set_vcl */
+
+	dsi_generic_write_seq(dsi, 0xc1, 0x01);		/* number of lines */
+	dsi_generic_write_seq(dsi, 0xc2, 0x08);		/* number of fp lines */
+	dsi_generic_write_seq(dsi, 0xc3, 0x04);		/* gateset(1) */
+	dsi_generic_write_seq(dsi, 0xc4, 0x4c);		/* 1h period */
+	dsi_generic_write_seq(dsi, 0xc5, 0x03);		/* source precharge */
+	dsi_generic_write_seq(dsi, 0xc6, 0xc4, 0x04);	/* source precharge timing */
+	dsi_generic_write_seq(dsi, 0xc7, 0x00);		/* source level */
+	dsi_generic_write_seq(dsi, 0xc8, 0x02);		/* number of bp lines */
+	dsi_generic_write_seq(dsi, 0xc9, 0x10);		/* gateset(2) */
+	dsi_generic_write_seq(dsi, 0xca, 0x04, 0x04);	/* gateset(3) */
+	dsi_generic_write_seq(dsi, 0xcb, 0x03);		/* gateset(4) */
+	dsi_generic_write_seq(dsi, 0xcc, 0x12);		/* gateset(5) */
+	dsi_generic_write_seq(dsi, 0xcd, 0x12);		/* gateset(6) */
+	dsi_generic_write_seq(dsi, 0xce, 0x30);		/* gateset(7) */
+	dsi_generic_write_seq(dsi, 0xcf, 0x30);		/* gateset(8) */
+	dsi_generic_write_seq(dsi, 0xd0, 0x40);		/* gateset(9) */
+	dsi_generic_write_seq(dsi, 0xd1, 0x22);		/* flhw */
+	dsi_generic_write_seq(dsi, 0xd2, 0x22);		/* vckhw */
+	dsi_generic_write_seq(dsi, 0xd3, 0x04);		/* flt */
+	dsi_generic_write_seq(dsi, 0xd4, 0x14);		/* tctrl */
+	dsi_generic_write_seq(dsi, 0xd6, 0x02);		/* dotinv */
+	dsi_generic_write_seq(dsi, 0xd7, 0x00);		/* on/off sequence period */
+
+	dsi_generic_write_seq(dsi, 0xd8, 0x01, 0x05, 0x06, 0x0d,
+			      0x18, 0x09, 0x22, 0x23, 0x00);		/* ponseqa */
+	dsi_generic_write_seq(dsi, 0xd9, 0x24, 0x01);			/* ponseqb */
+	dsi_generic_write_seq(dsi, 0xde, 0x09, 0x0f, 0x21, 0x12,
+			      0x04);					/* ponseqc */
+
+	dsi_generic_write_seq(dsi, 0xdf, 0x02, 0x06, 0x06, 0x06,
+			      0x06, 0x00);				/* pofseqa */
+	dsi_generic_write_seq(dsi, 0xe0, 0x01);				/* pofseqb */
+
+	ret = mipi_dsi_dcs_set_display_brightness(dsi, 0xff);
+	if (ret) {
+		log_debug("%s: failed to set display brightness: %d\n", __func__, ret);
+		return ret;
+	}
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x40);
+
+	dsi_generic_write_seq(dsi, 0xe2, 0x00, 0x00);		/* cabc pwm */
+	dsi_generic_write_seq(dsi, 0xe3, 0x03);			/* cabc */
+	dsi_generic_write_seq(dsi, 0xe4, 0x66, 0x7b, 0x90, 0xa5,
+			      0xbb, 0xc7, 0xe1, 0xe5);		/* cabc brightness */
+	dsi_generic_write_seq(dsi, 0xe5, 0xc5, 0xc5, 0xc9, 0xc9,
+			      0xd1, 0xe1, 0xf1, 0xfe);		/* cabc brightness */
+	dsi_generic_write_seq(dsi, 0xe7, 0x2a);			/* cabc */
+	dsi_generic_write_seq(dsi, 0xe8, 0x00);			/* brt_rev */
+	dsi_generic_write_seq(dsi, 0xe9, 0x00);			/* tefreq */
+
+	dsi_generic_write_seq(dsi, 0xea, 0x01);			/* high speed ram */
+
+	dsi_generic_write_seq(dsi, 0xeb, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r pos */
+	dsi_generic_write_seq(dsi, 0xec, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting r neg */
+	dsi_generic_write_seq(dsi, 0xed, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g pos */
+	dsi_generic_write_seq(dsi, 0xee, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting g neg */
+	dsi_generic_write_seq(dsi, 0xef, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b pos */
+	dsi_generic_write_seq(dsi, 0xf0, 0x00, 0x33, 0x0e, 0x15,
+			      0xb7, 0x78, 0x88, 0x0f);		/* gamma setting b neg */
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret) {
+		log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	mdelay(110);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret) {
+		log_debug("%s: failed to set display on: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int hitachi_tx10d07vm0baa_set_backlight(struct udevice *dev, int percent)
+{
+	struct hitachi_tx10d07vm0baa_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = backlight_enable(priv->backlight);
+	if (ret)
+		return ret;
+
+	return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int hitachi_tx10d07vm0baa_timings(struct udevice *dev,
+					 struct display_timing *timing)
+{
+	memcpy(timing, &default_timing, sizeof(*timing));
+	return 0;
+}
+
+static int hitachi_tx10d07vm0baa_of_to_plat(struct udevice *dev)
+{
+	struct hitachi_tx10d07vm0baa_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_debug("%s: cannot get backlight: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "avci-supply", &priv->avci);
+	if (ret) {
+		log_debug("%s: cannot get avci-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "iovcc-supply", &priv->iovcc);
+	if (ret) {
+		log_debug("%s: cannot get iovcc-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0,
+				   &priv->reset_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: cannot decode reset-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int hitachi_tx10d07vm0baa_hw_init(struct udevice *dev)
+{
+	struct hitachi_tx10d07vm0baa_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret) {
+		log_debug("%s: error entering reset (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->iovcc, 1);
+	if (ret) {
+		log_debug("%s: enabling iovcc-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->avci, 1);
+	if (ret) {
+		log_debug("%s: enabling avci-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	mdelay(25);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	mdelay(5);
+
+	return 0;
+}
+
+static int hitachi_tx10d07vm0baa_probe(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 2;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
+
+	return hitachi_tx10d07vm0baa_hw_init(dev);
+}
+
+static const struct panel_ops hitachi_tx10d07vm0baa_ops = {
+	.enable_backlight	= hitachi_tx10d07vm0baa_enable_backlight,
+	.set_backlight		= hitachi_tx10d07vm0baa_set_backlight,
+	.get_display_timing	= hitachi_tx10d07vm0baa_timings,
+};
+
+static const struct udevice_id hitachi_tx10d07vm0baa_ids[] = {
+	{ .compatible = "hit,tx10d07vm0baa" },
+	{ }
+};
+
+U_BOOT_DRIVER(hitachi_tx10d07vm0baa) = {
+	.name		= "hitachi_tx10d07vm0baa",
+	.id		= UCLASS_PANEL,
+	.of_match	= hitachi_tx10d07vm0baa_ids,
+	.ops		= &hitachi_tx10d07vm0baa_ops,
+	.of_to_plat	= hitachi_tx10d07vm0baa_of_to_plat,
+	.probe		= hitachi_tx10d07vm0baa_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct hitachi_tx10d07vm0baa_priv),
+};
diff --git a/drivers/video/lg-lh400wv3-sd04.c b/drivers/video/lg-lh400wv3-sd04.c
new file mode 100644
index 00000000000..0385b39867f
--- /dev/null
+++ b/drivers/video/lg-lh400wv3-sd04.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * LG LH400WV3-SD04 DSI panel driver
+ *
+ * Copyright (c) 2025 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <backlight.h>
+#include <dm.h>
+#include <panel.h>
+#include <log.h>
+#include <mipi_dsi.h>
+#include <linux/delay.h>
+#include <power/regulator.h>
+#include <asm/gpio.h>
+
+struct lg_lh400wv3_priv {
+	struct udevice *avci;
+	struct udevice *iovcc;
+
+	struct udevice *backlight;
+
+	struct gpio_desc reset_gpio;
+};
+
+static struct display_timing default_timing = {
+	.pixelclock.typ		= 29816000,
+	.hactive.typ		= 480,
+	.hfront_porch.typ	= 10,
+	.hback_porch.typ	= 10,
+	.hsync_len.typ		= 10,
+	.vactive.typ		= 800,
+	.vfront_porch.typ	= 4,
+	.vback_porch.typ	= 4,
+	.vsync_len.typ		= 4,
+};
+
+#define dsi_generic_write_seq(dsi, cmd, seq...) do {			\
+		static const u8 b[] = { cmd, seq };			\
+		int ret;						\
+		ret = mipi_dsi_dcs_write_buffer(dsi, b, ARRAY_SIZE(b));	\
+		if (ret < 0)						\
+			return ret;					\
+	} while (0)
+
+static int lg_lh400wv3_enable_backlight(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+	struct mipi_dsi_device *dsi = plat->device;
+	int ret;
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_EXIT_INVERT_MODE);
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_TEAR_ON);
+
+	ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
+					    MIPI_DCS_PIXEL_FMT_24BIT << 4);
+	if (ret < 0) {
+		log_debug("%s: failed to set pixel format: %d\n", __func__, ret);
+		return ret;
+	}
+
+	dsi_generic_write_seq(dsi, 0xb2, 0x00, 0xc8);
+	dsi_generic_write_seq(dsi, 0xb3, 0x00);
+	dsi_generic_write_seq(dsi, 0xb4, 0x04);
+	dsi_generic_write_seq(dsi, 0xb5, 0x42, 0x10, 0x10, 0x00, 0x20);
+	dsi_generic_write_seq(dsi, 0xb6, 0x0b, 0x0f, 0x3c, 0x13, 0x13, 0xe8);
+	dsi_generic_write_seq(dsi, 0xb7, 0x4c, 0x06, 0x0c, 0x00, 0x00);
+
+	dsi_generic_write_seq(dsi, 0xc0, 0x01, 0x11);
+	dsi_generic_write_seq(dsi, 0xc3, 0x07, 0x03, 0x04, 0x04, 0x04);
+	dsi_generic_write_seq(dsi, 0xc4, 0x12, 0x24, 0x18, 0x18, 0x02, 0x49);
+	dsi_generic_write_seq(dsi, 0xc5, 0x65);
+	dsi_generic_write_seq(dsi, 0xc6, 0x41, 0x63);
+
+	dsi_generic_write_seq(dsi, 0xd0, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
+	dsi_generic_write_seq(dsi, 0xd1, 0x00, 0x46, 0x74, 0x32, 0x1d, 0x03, 0x51, 0x15, 0x04);
+	dsi_generic_write_seq(dsi, 0xd2, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
+	dsi_generic_write_seq(dsi, 0xd3, 0x00, 0x46, 0x74, 0x32, 0x1f, 0x03, 0x51, 0x15, 0x04);
+	dsi_generic_write_seq(dsi, 0xd4, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
+	dsi_generic_write_seq(dsi, 0xd5, 0x01, 0x46, 0x74, 0x25, 0x00, 0x03, 0x51, 0x15, 0x04);
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, 0x00, 0x00, 0x01, 0xdf);
+	dsi_generic_write_seq(dsi, MIPI_DCS_SET_PAGE_ADDRESS, 0x00, 0x00, 0x03, 0x1f);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to exit sleep mode: %d\n", __func__, ret);
+		return ret;
+	}
+
+	mdelay(120);
+
+	dsi_generic_write_seq(dsi, MIPI_DCS_WRITE_MEMORY_START);
+
+	ret = mipi_dsi_dcs_set_display_on(dsi);
+	if (ret < 0) {
+		log_debug("%s: failed to set display on: %d\n", __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int lg_lh400wv3_set_backlight(struct udevice *dev, int percent)
+{
+	struct lg_lh400wv3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = backlight_enable(priv->backlight);
+	if (ret)
+		return ret;
+
+	return backlight_set_brightness(priv->backlight, percent);
+}
+
+static int lg_lh400wv3_timings(struct udevice *dev, struct display_timing *timing)
+{
+	memcpy(timing, &default_timing, sizeof(*timing));
+	return 0;
+}
+
+static int lg_lh400wv3_of_to_plat(struct udevice *dev)
+{
+	struct lg_lh400wv3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+					   "backlight", &priv->backlight);
+	if (ret) {
+		log_debug("%s: cannot get backlight: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "avci-supply", &priv->avci);
+	if (ret) {
+		log_debug("%s: cannot get avci-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = device_get_supply_regulator(dev, "iovcc-supply", &priv->iovcc);
+	if (ret) {
+		log_debug("%s: cannot get iovcc-supply: ret = %d\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "reset-gpios", 0,
+				   &priv->reset_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: cannot decode reset-gpios (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int lg_lh400wv3_hw_init(struct udevice *dev)
+{
+	struct lg_lh400wv3_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 1);
+	if (ret) {
+		log_debug("%s: error entering reset (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->iovcc, 1);
+	if (ret) {
+		log_debug("%s: enabling iovcc-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	ret = regulator_set_enable_if_allowed(priv->avci, 1);
+	if (ret) {
+		log_debug("%s: enabling avci-supply failed (%d)\n",
+			  __func__, ret);
+		return ret;
+	}
+
+	mdelay(1);
+
+	ret = dm_gpio_set_value(&priv->reset_gpio, 0);
+	if (ret) {
+		log_debug("%s: error exiting reset (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	mdelay(10);
+
+	return 0;
+}
+
+static int lg_lh400wv3_probe(struct udevice *dev)
+{
+	struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
+
+	/* fill characteristics of DSI data link */
+	plat->lanes = 2;
+	plat->format = MIPI_DSI_FMT_RGB888;
+	plat->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
+
+	return lg_lh400wv3_hw_init(dev);
+}
+
+static const struct panel_ops lg_lh400wv3_ops = {
+	.enable_backlight	= lg_lh400wv3_enable_backlight,
+	.set_backlight		= lg_lh400wv3_set_backlight,
+	.get_display_timing	= lg_lh400wv3_timings,
+};
+
+static const struct udevice_id lg_lh400wv3_ids[] = {
+	{ .compatible = "lg,lh400wv3-sd04" },
+	{ }
+};
+
+U_BOOT_DRIVER(lg_lh400wv3) = {
+	.name		= "lg_lh400wv3",
+	.id		= UCLASS_PANEL,
+	.of_match	= lg_lh400wv3_ids,
+	.ops		= &lg_lh400wv3_ops,
+	.of_to_plat	= lg_lh400wv3_of_to_plat,
+	.probe		= lg_lh400wv3_probe,
+	.plat_auto	= sizeof(struct mipi_dsi_panel_plat),
+	.priv_auto	= sizeof(struct lg_lh400wv3_priv),
+};
diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig
index 1a328407b13..f32972d937e 100644
--- a/drivers/video/tegra/Kconfig
+++ b/drivers/video/tegra/Kconfig
@@ -42,6 +42,16 @@ config TEGRA_BACKLIGHT_PWM
 	   Enable support for the Display Controller dependent PWM backlight
 	   found in the Tegra SoC and usually used with DSI panels.
 
+config TEGRA_8BIT_CPU_BRIDGE
+	bool "Enable 8 bit panel communication protocol for Tegra 20/30"
+	depends on VIDEO_BRIDGE && DM_GPIO
+	select VIDEO_TEGRA
+	select VIDEO_MIPI_DSI
+	help
+	   Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control
+	   protocol. This option allows use it as a MIPI DSI bridge to
+	   set up and control compatible panel.
+
 config VIDEO_TEGRA124
 	bool "Enable video support on Tegra124"
 	imply VIDEO_DAMAGE
diff --git a/drivers/video/tegra/Makefile b/drivers/video/tegra/Makefile
index 3c50a0ba3c3..4995c93a8af 100644
--- a/drivers/video/tegra/Makefile
+++ b/drivers/video/tegra/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_VIDEO_TEGRA) += dc.o
 obj-$(CONFIG_VIDEO_DSI_TEGRA) += dsi.o mipi.o mipi-phy.o
 obj-$(CONFIG_VIDEO_HDMI_TEGRA) += hdmi.o
 obj-$(CONFIG_TEGRA_BACKLIGHT_PWM) += dc-pwm-backlight.o
+obj-$(CONFIG_TEGRA_8BIT_CPU_BRIDGE) += cpu-bridge.o
 
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/tegra/cpu-bridge.c b/drivers/video/tegra/cpu-bridge.c
new file mode 100644
index 00000000000..e5fefe028f0
--- /dev/null
+++ b/drivers/video/tegra/cpu-bridge.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
+ *
+ * This driver uses 8-bit CPU interface found in Tegra 2
+ * and Tegra 3 to drive MIPI DSI panel.
+ */
+
+#include <dm.h>
+#include <dm/ofnode_graph.h>
+#include <log.h>
+#include <mipi_display.h>
+#include <mipi_dsi.h>
+#include <backlight.h>
+#include <panel.h>
+#include <video_bridge.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+#include "dc.h"
+
+struct tegra_cpu_bridge_priv {
+	struct dc_ctlr *dc;
+
+	struct mipi_dsi_host host;
+	struct mipi_dsi_device device;
+
+	struct udevice *panel;
+	struct display_timing timing;
+
+	struct gpio_desc dc_gpio;
+	struct gpio_desc rw_gpio;
+	struct gpio_desc cs_gpio;
+
+	struct gpio_desc data_gpios[8];
+
+	u32 pixel_format;
+	u32 spi_init_seq[4];
+};
+
+#define TEGRA_CPU_BRIDGE_COMM 0
+#define TEGRA_CPU_BRIDGE_DATA 1
+
+static void tegra_cpu_bridge_write(struct tegra_cpu_bridge_priv *priv,
+				   u8 type, u8 value)
+{
+	int i;
+
+	dm_gpio_set_value(&priv->dc_gpio, type);
+
+	dm_gpio_set_value(&priv->cs_gpio, 0);
+	dm_gpio_set_value(&priv->rw_gpio, 0);
+
+	for (i = 0; i < 8; i++)
+		dm_gpio_set_value(&priv->data_gpios[i],
+				  (value >> i) & 0x1);
+
+	dm_gpio_set_value(&priv->cs_gpio, 1);
+	dm_gpio_set_value(&priv->rw_gpio, 1);
+
+	udelay(10);
+
+	log_debug("%s: type 0x%x, val 0x%x\n",
+		  __func__, type, value);
+}
+
+static ssize_t tegra_cpu_bridge_transfer(struct mipi_dsi_host *host,
+					 const struct mipi_dsi_msg *msg)
+{
+	struct udevice *dev = (struct udevice *)host->dev;
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+	u8 command = *(u8 *)msg->tx_buf;
+	const u8 *data = msg->tx_buf;
+	int i;
+
+	tegra_cpu_bridge_write(priv, TEGRA_CPU_BRIDGE_COMM, command);
+
+	for (i = 1; i < msg->tx_len; i++)
+		tegra_cpu_bridge_write(priv, TEGRA_CPU_BRIDGE_DATA, data[i]);
+
+	return 0;
+}
+
+static const struct mipi_dsi_host_ops tegra_cpu_bridge_host_ops = {
+	.transfer	= tegra_cpu_bridge_transfer,
+};
+
+static int tegra_cpu_bridge_get_format(enum mipi_dsi_pixel_format format, u32 *fmt)
+{
+	switch (format) {
+	case MIPI_DSI_FMT_RGB888:
+	case MIPI_DSI_FMT_RGB666_PACKED:
+		*fmt = BASE_COLOR_SIZE_888;
+		break;
+
+	case MIPI_DSI_FMT_RGB666:
+		*fmt = BASE_COLOR_SIZE_666;
+		break;
+
+	case MIPI_DSI_FMT_RGB565:
+		*fmt = BASE_COLOR_SIZE_565;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra_cpu_bridge_attach(struct udevice *dev)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+	struct dc_disp_reg *disp = &priv->dc->disp;
+	struct dc_cmd_reg *cmd = &priv->dc->cmd;
+	struct dc_com_reg *com = &priv->dc->com;
+	u32 value;
+	int ret;
+
+	writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &cmd->disp_cmd);
+	writel(0, &disp->disp_win_opt);
+	writel(GENERAL_UPDATE, &cmd->state_ctrl);
+	writel(GENERAL_ACT_REQ, &cmd->state_ctrl);
+
+	/* TODO: parametrize if needed */
+	writel(V_PULSE1_ENABLE, &disp->disp_signal_opt0);
+	writel(PULSE_POLARITY_LOW, &disp->v_pulse1.v_pulse_ctrl);
+
+	writel(PULSE_END(1), &disp->v_pulse1.v_pulse_pos[V_PULSE0_POSITION_A]);
+	writel(0, &disp->v_pulse1.v_pulse_pos[V_PULSE0_POSITION_B]);
+	writel(0, &disp->v_pulse1.v_pulse_pos[V_PULSE0_POSITION_C]);
+
+	ret = dev_read_u32_array(dev, "nvidia,init-sequence", priv->spi_init_seq, 4);
+	if (!ret) {
+		value = 1 << FRAME_INIT_SEQ_CYCLES_SHIFT |
+			DC_SIGNAL_VPULSE1 << INIT_SEQ_DC_SIGNAL_SHIFT |
+			INIT_SEQUENCE_MODE_PLCD | SEND_INIT_SEQUENCE;
+		writel(value, &disp->seq_ctrl);
+
+		writel(priv->spi_init_seq[0], &disp->spi_init_seq_data_a);
+		writel(priv->spi_init_seq[1], &disp->spi_init_seq_data_b);
+		writel(priv->spi_init_seq[2], &disp->spi_init_seq_data_c);
+		writel(priv->spi_init_seq[3], &disp->spi_init_seq_data_d);
+	}
+
+	value = readl(&cmd->disp_cmd);
+	value &= ~CTRL_MODE_MASK;
+	value |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT;
+	writel(value, &cmd->disp_cmd);
+
+	/* set LDC pin to V Pulse 1 */
+	value = readl(&com->pin_output_sel[6]) | LDC_OUTPUT_SELECT_V_PULSE1;
+	writel(value, &com->pin_output_sel[6]);
+
+	value = readl(&disp->disp_interface_ctrl);
+	value |= DATA_ALIGNMENT_LSB << DATA_ALIGNMENT_SHIFT;
+	writel(value, &disp->disp_interface_ctrl);
+
+	value = SC_H_QUALIFIER_NONE << SC1_H_QUALIFIER_SHIFT |
+		SC_V_QUALIFIER_VACTIVE << SC0_V_QUALIFIER_SHIFT |
+		SC_H_QUALIFIER_HACTIVE << SC0_H_QUALIFIER_SHIFT;
+	writel(value, &disp->shift_clk_opt);
+
+	value = readl(&disp->disp_color_ctrl);
+	value |= priv->pixel_format;
+	writel(value, &disp->disp_color_ctrl);
+
+	/* Perform panel setup */
+	panel_enable_backlight(priv->panel);
+
+	dm_gpio_set_value(&priv->cs_gpio, 0);
+
+	dm_gpio_free(dev, &priv->dc_gpio);
+	dm_gpio_free(dev, &priv->rw_gpio);
+	dm_gpio_free(dev, &priv->cs_gpio);
+
+	gpio_free_list(dev, priv->data_gpios, 8);
+
+	return 0;
+}
+
+static int tegra_cpu_bridge_set_panel(struct udevice *dev, int percent)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+
+	return panel_set_backlight(priv->panel, percent);
+}
+
+static int tegra_cpu_bridge_panel_timings(struct udevice *dev,
+					  struct display_timing *timing)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+
+	memcpy(timing, &priv->timing, sizeof(*timing));
+
+	return 0;
+}
+
+static int tegra_cpu_bridge_hw_init(struct udevice *dev)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+
+	dm_gpio_set_value(&priv->cs_gpio, 1);
+
+	dm_gpio_set_value(&priv->rw_gpio, 1);
+	dm_gpio_set_value(&priv->dc_gpio, 0);
+
+	return 0;
+}
+
+static int tegra_cpu_bridge_get_links(struct udevice *dev)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+	int i, ret;
+
+	u32 num = ofnode_graph_get_port_count(dev_ofnode(dev));
+
+	for (i = 0; i < num; i++) {
+		ofnode remote = ofnode_graph_get_remote_node(dev_ofnode(dev), i, -1);
+
+		/* Look for DC source */
+		if (ofnode_name_eq(remote, "rgb")) {
+			ofnode dc = ofnode_get_parent(remote);
+
+			priv->dc = (struct dc_ctlr *)ofnode_get_addr(dc);
+			if (!priv->dc) {
+				log_err("%s: failed to get DC controller\n", __func__);
+				return -EINVAL;
+			}
+		}
+
+		/* Look for driven panel */
+		ret = uclass_get_device_by_ofnode(UCLASS_PANEL, remote, &priv->panel);
+		if (!ret)
+			return 0;
+	}
+
+	/* If this point is reached, no panels were found */
+	return -ENODEV;
+}
+
+static int tegra_cpu_bridge_probe(struct udevice *dev)
+{
+	struct tegra_cpu_bridge_priv *priv = dev_get_priv(dev);
+	struct mipi_dsi_device *device = &priv->device;
+	struct mipi_dsi_panel_plat *mipi_plat;
+	int ret;
+
+	ret = tegra_cpu_bridge_get_links(dev);
+	if (ret) {
+		log_debug("%s: links not found, ret %d\n", __func__, ret);
+		return ret;
+	}
+
+	panel_get_display_timing(priv->panel, &priv->timing);
+
+	mipi_plat = dev_get_plat(priv->panel);
+	mipi_plat->device = device;
+
+	priv->host.dev = (struct device *)dev;
+	priv->host.ops = &tegra_cpu_bridge_host_ops;
+
+	device->host = &priv->host;
+	device->lanes = mipi_plat->lanes;
+	device->format = mipi_plat->format;
+	device->mode_flags = mipi_plat->mode_flags;
+
+	tegra_cpu_bridge_get_format(device->format, &priv->pixel_format);
+
+	/* get control gpios */
+	ret = gpio_request_by_name(dev, "dc-gpios", 0,
+				   &priv->dc_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not decode dc-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "rw-gpios", 0,
+				   &priv->rw_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not decode rw-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	ret = gpio_request_by_name(dev, "cs-gpios", 0,
+				   &priv->cs_gpio, GPIOD_IS_OUT);
+	if (ret) {
+		log_debug("%s: could not decode cs-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	/* get data gpios */
+	ret = gpio_request_list_by_name(dev, "data-gpios",
+					priv->data_gpios, 8,
+					GPIOD_IS_OUT);
+	if (ret < 0) {
+		log_debug("%s: could not decode data-gpios (%d)\n", __func__, ret);
+		return ret;
+	}
+
+	return tegra_cpu_bridge_hw_init(dev);
+}
+
+static const struct video_bridge_ops tegra_cpu_bridge_ops = {
+	.attach			= tegra_cpu_bridge_attach,
+	.set_backlight		= tegra_cpu_bridge_set_panel,
+	.get_display_timing	= tegra_cpu_bridge_panel_timings,
+};
+
+static const struct udevice_id tegra_cpu_bridge_ids[] = {
+	{ .compatible = "nvidia,tegra-8bit-cpu" },
+	{ }
+};
+
+U_BOOT_DRIVER(tegra_8bit_cpu) = {
+	.name		= "tegra_8bit_cpu",
+	.id		= UCLASS_VIDEO_BRIDGE,
+	.of_match	= tegra_cpu_bridge_ids,
+	.ops		= &tegra_cpu_bridge_ops,
+	.bind		= dm_scan_fdt_dev,
+	.probe		= tegra_cpu_bridge_probe,
+	.priv_auto	= sizeof(struct tegra_cpu_bridge_priv),
+};