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| author | Tom Rini <trini@konsulko.com> | 2021-05-19 11:50:25 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-05-19 11:50:25 -0400 |
| commit | 27c2236f8acfa311eed2c8f8d210824fadd25483 (patch) | |
| tree | c0431a281fe967221f6e8c839779e58e5d8d8b8a /include/dt-bindings | |
| parent | 428bec7cf956c3558bbdfda4d2ba23beb73a68ba (diff) | |
| parent | c0e6feeb343f8643376610fb3afd9eb8bcea6aad (diff) | |
Merge tag 'xilinx-for-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.07-rc3
ZynqMP:
- Syncup DT with Linux kernel
- Fix mmc mini configurations via DT
- Add pinctrl/psgtr description to DTs
- Add DTs for Kria boards
- Enable RTC and Time commands
Versal:
- Fix early BSS section location
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h new file mode 100644 index 00000000000..cdb215734bd --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * MIO pin configuration defines for Xilinx ZynqMP + * + * Copyright (C) 2020 Xilinx, Inc. + */ + +#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H +#define _DT_BINDINGS_PINCTRL_ZYNQMP_H + +/* Bit value for different voltage levels */ +#define IO_STANDARD_LVCMOS33 0 +#define IO_STANDARD_LVCMOS18 1 + +/* Bit values for Slew Rates */ +#define SLEW_RATE_FAST 0 +#define SLEW_RATE_SLOW 1 + +#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ |