diff options
| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-03 10:43:23 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:15:26 -0600 |
| commit | a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc (patch) | |
| tree | a3a1f15b0b516f487ec929908cc501f4939d1626 /include/dt-bindings | |
| parent | 6dfa991204a6fe033a5f0c49ff4f1d6e8af3ed7c (diff) | |
clk: mediatek: mt7622: add missing clock MUX1_SEL
Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to
match the upstream clk ID order in preparation for OF_UPSTREAM.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/mt7622-clk.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 569bfce0d05..0820fab0a22 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -120,12 +120,13 @@ /* INFRACFG */ -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_AUDIO_PD 1 -#define CLK_INFRA_IRRX_PD 2 -#define CLK_INFRA_APXGPT_PD 3 -#define CLK_INFRA_PMIC_PD 4 -#define CLK_INFRA_TRNG 5 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_AUDIO_PD 2 +#define CLK_INFRA_IRRX_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6 /* PERICFG */ |