diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-04-03 19:07:02 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:39 +0800 |
| commit | 9acad2b4c7214bb423a6221b67b0d7ea37edbdf7 (patch) | |
| tree | 97149ff2ca69eabffcd2b78b76d60eefd9dadd81 /include/linux/intel-smc.h | |
| parent | ef16992e3eab0eaa3c194fffd65bd8cc89050388 (diff) | |
arm: socfpga: soc64: Update reset manager registers for F2S bridge
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.
Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc
These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'include/linux/intel-smc.h')
| -rw-r--r-- | include/linux/intel-smc.h | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/include/linux/intel-smc.h b/include/linux/intel-smc.h index a54eff43add..6455335bae4 100644 --- a/include/linux/intel-smc.h +++ b/include/linux/intel-smc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2017-2018, Intel Corporation + * Copyright (C) 2025 Altera Corporation <www.altera.com> */ #ifndef __INTEL_SMC_H @@ -482,10 +483,16 @@ INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE) * Call register usage: * a0 INTEL_SIP_SMC_HPS_SET_BRIDGES * a1 Set bridges status: - * 0 - Disable - * 1 - Enable - * a2-7 not used - * + * Bit 0: 0 - Disable, 1 - Enable + * Bit 1: 1 - Has mask value in a2 + * a2 Mask value + * Bit 0: soc2fpga + * Bit 1: lwhps2fpga + * Bit 2: fpga2soc + * Bit 3: f2sdram0 (For Stratix 10 only) + * Bit 4: f2sdram1 (For Stratix 10 only) + * Bit 5: f2sdram2 (For Stratix 10 only) + * a3-7 not used * Return status * a0 INTEL_SIP_SMC_STATUS_OK */ |