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| author | Tom Rini <trini@konsulko.com> | 2025-01-22 11:23:35 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-01-22 11:23:35 -0600 |
| commit | 2eed5a1ff36217372e19f7513bd07077fc76718a (patch) | |
| tree | e98aadc2d4d04fc12504d00db17c4edc38bbb59d /include/pci.h | |
| parent | 380b32f54f4b30f6f9b430c5d73d8b12f90f2918 (diff) | |
| parent | 599a1f9076d34c29d3683e0f833706478d62d9e0 (diff) | |
Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon
The highlights are:
* Fixed boot regression due to broken memory parsing
* Enable HW RNG and KASLR on all platforms
* Add support for Snapdragon X1 Elite hardware (clk/pinctrl)
* Add support for QCS9100 ride automotive development platform (clk/ufs)
* Add support for PCIe on SM8550, SM8650 and X1E
* Implement software debounce for PMIC buttons
Additionally, some minor improvements to "ufetch" have been pulled in:
* Show CPU architecture (arm/mips/etc)
* Make CONFIG_BLK optional
* Fix 32-bit support
Diffstat (limited to 'include/pci.h')
| -rw-r--r-- | include/pci.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/pci.h b/include/pci.h index 5fea815b48c..4b0facd6dcf 100644 --- a/include/pci.h +++ b/include/pci.h @@ -390,6 +390,9 @@ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ +#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ +#define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ +#define PCI_EXP_LNKCAP_ASPM_L1 0x00000800 /* ASPM L1 Support */ #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ #define PCI_EXP_LNKCTL 16 /* Link Control */ #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */ @@ -404,6 +407,7 @@ #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_RTCTL 28 /* Root Control */ #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ |