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| author | Tom Rini <trini@konsulko.com> | 2017-08-04 07:23:32 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-08-04 07:23:32 -0400 |
| commit | fe84c48eeb8e9cb0b8b80a4c0a53bb089adff9af (patch) | |
| tree | 7b3d2b47abc9b9f11f0e79a591f590050912c68a /include/zynqmppl.h | |
| parent | 217324b23c4a73420633068efcdc396682894b1b (diff) | |
| parent | df1cd46fb84922735e1c12f54b7202b0268dcddd (diff) | |
Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2017.09
Zynq:
- Add Z-Turn board support
fpga:
- Remove intermediate buffer from code
Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
Diffstat (limited to 'include/zynqmppl.h')
| -rw-r--r-- | include/zynqmppl.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/zynqmppl.h b/include/zynqmppl.h index fb5200ec84a..4c8c2f88f04 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -20,7 +20,7 @@ #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 -#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xe << ZYNQMP_CSU_IDCODE_SVD_SHIFT) +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) extern struct xilinx_fpga_op zynqmp_op; |