diff options
| author | Christian Marangi <ansuelsmth@gmail.com> | 2024-08-03 10:43:25 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-08-19 16:15:26 -0600 |
| commit | 105c78844a6cf72eefbfd614fc52da92bc0341f1 (patch) | |
| tree | 0552b2d21de8843ede60460e97476ed57964a6fa /include | |
| parent | a776493f4b4b51515db456e635709a93e256dacd (diff) | |
clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/mt7622-clk.h | 59 |
1 files changed, 30 insertions, 29 deletions
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 4b6501c1020..cd11a1c901e 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -130,35 +130,36 @@ /* PERICFG */ -#define CLK_PERI_THERM_PD 0 -#define CLK_PERI_PWM1_PD 1 -#define CLK_PERI_PWM2_PD 2 -#define CLK_PERI_PWM3_PD 3 -#define CLK_PERI_PWM4_PD 4 -#define CLK_PERI_PWM5_PD 5 -#define CLK_PERI_PWM6_PD 6 -#define CLK_PERI_PWM7_PD 7 -#define CLK_PERI_PWM_PD 8 -#define CLK_PERI_AP_DMA_PD 9 -#define CLK_PERI_MSDC30_0_PD 10 -#define CLK_PERI_MSDC30_1_PD 11 -#define CLK_PERI_UART0_PD 12 -#define CLK_PERI_UART1_PD 13 -#define CLK_PERI_UART2_PD 14 -#define CLK_PERI_UART3_PD 15 -#define CLK_PERI_UART4_PD 16 -#define CLK_PERI_BTIF_PD 17 -#define CLK_PERI_I2C0_PD 18 -#define CLK_PERI_I2C1_PD 19 -#define CLK_PERI_I2C2_PD 20 -#define CLK_PERI_SPI1_PD 21 -#define CLK_PERI_AUXADC_PD 22 -#define CLK_PERI_SPI0_PD 23 -#define CLK_PERI_SNFI_PD 24 -#define CLK_PERI_NFI_PD 25 -#define CLK_PERI_NFIECC_PD 26 -#define CLK_PERI_FLASH_PD 27 -#define CLK_PERI_IRTX_PD 28 +#define CLK_PERIBUS_SEL 0 +#define CLK_PERI_THERM_PD 1 +#define CLK_PERI_PWM1_PD 2 +#define CLK_PERI_PWM2_PD 3 +#define CLK_PERI_PWM3_PD 4 +#define CLK_PERI_PWM4_PD 5 +#define CLK_PERI_PWM5_PD 6 +#define CLK_PERI_PWM6_PD 7 +#define CLK_PERI_PWM7_PD 8 +#define CLK_PERI_PWM_PD 9 +#define CLK_PERI_AP_DMA_PD 10 +#define CLK_PERI_MSDC30_0_PD 11 +#define CLK_PERI_MSDC30_1_PD 12 +#define CLK_PERI_UART0_PD 13 +#define CLK_PERI_UART1_PD 14 +#define CLK_PERI_UART2_PD 15 +#define CLK_PERI_UART3_PD 16 +#define CLK_PERI_UART4_PD 17 +#define CLK_PERI_BTIF_PD 18 +#define CLK_PERI_I2C0_PD 19 +#define CLK_PERI_I2C1_PD 20 +#define CLK_PERI_I2C2_PD 21 +#define CLK_PERI_SPI1_PD 22 +#define CLK_PERI_AUXADC_PD 23 +#define CLK_PERI_SPI0_PD 24 +#define CLK_PERI_SNFI_PD 25 +#define CLK_PERI_NFI_PD 26 +#define CLK_PERI_NFIECC_PD 27 +#define CLK_PERI_FLASH_PD 28 +#define CLK_PERI_IRTX_PD 29 /* APMIXEDSYS */ |