Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.07-rc1

microblaze:
- Add support for reserved memory

xilinx:
- Update FRU code with MAC reading

zynqmp:
- Remove double AMS setting
- DT updates (mostly for SOMs)
- Add support for zcu106 rev 1.0

zynq:
- Update nand binding

nand:
- Aligned zynq_nand to upstream DT binding

net:
- Add support for ethernet-phy-id

mmc:
- Workaround CD in zynq_sdhci driver also for ZynqMP
- Add support for dynamic/run-time SD config for SOMs

gpio:
- Add driver for slg7xl45106

firmware:
- Add support for dynamic SD config

power-domain:
- Update zynqmp driver with the latest firmware

video:
- Add skeleton driver for DP and DPDMA

i2c:
- Fix i2c to work with QEMU

pinctrl:
- Add driver for zynqmp pinctrl driver

5 files changed, 139 insertions, 25 deletions

diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 0cb324c8b0c..744dffe0a2d 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -895,6 +895,19 @@ int ofnode_read_pci_addr(ofnode node, enum fdt_pci_space type,
 int ofnode_read_pci_vendev(ofnode node, u16 *vendor, u16 *device);
 
 /**
+ * ofnode_read_eth_phy_id() - look up eth phy vendor and device id
+ *
+ * Look at the compatible property of a device node that represents a eth phy
+ * device and extract phy vendor id and device id from it.
+ *
+ * @param node		node to examine
+ * @param vendor	vendor id of the eth phy device
+ * @param device	device id of the eth phy device
+ * @return 0 if ok, negative on error
+ */
+int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device);
+
+/**
  * ofnode_read_addr_cells() - Get the number of address cells for a node
  *
  * This walks back up the tree to find the closest #address-cells property
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index 8b869c4fbfb..a09b242fd99 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -7,7 +7,7 @@
 #define __PINCTRL_H
 
 #define PINNAME_SIZE	10
-#define PINMUX_SIZE	40
+#define PINMUX_SIZE	80
 
 /**
  * struct pinconf_param - pin config parameters
@@ -453,30 +453,30 @@ struct pinctrl_ops {
  *	presented using the packed format.
  */
 enum pin_config_param {
-	PIN_CONFIG_BIAS_BUS_HOLD,
-	PIN_CONFIG_BIAS_DISABLE,
-	PIN_CONFIG_BIAS_HIGH_IMPEDANCE,
-	PIN_CONFIG_BIAS_PULL_DOWN,
-	PIN_CONFIG_BIAS_PULL_PIN_DEFAULT,
-	PIN_CONFIG_BIAS_PULL_UP,
-	PIN_CONFIG_DRIVE_OPEN_DRAIN,
-	PIN_CONFIG_DRIVE_OPEN_SOURCE,
-	PIN_CONFIG_DRIVE_PUSH_PULL,
-	PIN_CONFIG_DRIVE_STRENGTH,
-	PIN_CONFIG_DRIVE_STRENGTH_UA,
-	PIN_CONFIG_INPUT_DEBOUNCE,
-	PIN_CONFIG_INPUT_ENABLE,
-	PIN_CONFIG_INPUT_SCHMITT,
-	PIN_CONFIG_INPUT_SCHMITT_ENABLE,
-	PIN_CONFIG_LOW_POWER_MODE,
-	PIN_CONFIG_OUTPUT_ENABLE,
-	PIN_CONFIG_OUTPUT,
-	PIN_CONFIG_POWER_SOURCE,
-	PIN_CONFIG_SLEEP_HARDWARE_STATE,
-	PIN_CONFIG_SLEW_RATE,
-	PIN_CONFIG_SKEW_DELAY,
-	PIN_CONFIG_END = 0x7F,
-	PIN_CONFIG_MAX = 0xFF,
+	PIN_CONFIG_BIAS_BUS_HOLD = 0,
+	PIN_CONFIG_BIAS_DISABLE = 1,
+	PIN_CONFIG_BIAS_HIGH_IMPEDANCE = 2,
+	PIN_CONFIG_BIAS_PULL_DOWN = 3,
+	PIN_CONFIG_BIAS_PULL_PIN_DEFAULT = 4,
+	PIN_CONFIG_BIAS_PULL_UP = 5,
+	PIN_CONFIG_DRIVE_OPEN_DRAIN = 6,
+	PIN_CONFIG_DRIVE_OPEN_SOURCE = 7,
+	PIN_CONFIG_DRIVE_PUSH_PULL = 8,
+	PIN_CONFIG_DRIVE_STRENGTH = 9,
+	PIN_CONFIG_DRIVE_STRENGTH_UA = 10,
+	PIN_CONFIG_INPUT_DEBOUNCE = 11,
+	PIN_CONFIG_INPUT_ENABLE = 12,
+	PIN_CONFIG_INPUT_SCHMITT = 13,
+	PIN_CONFIG_INPUT_SCHMITT_ENABLE = 14,
+	PIN_CONFIG_LOW_POWER_MODE = 15,
+	PIN_CONFIG_OUTPUT_ENABLE = 16,
+	PIN_CONFIG_OUTPUT = 17,
+	PIN_CONFIG_POWER_SOURCE = 18,
+	PIN_CONFIG_SLEEP_HARDWARE_STATE = 19,
+	PIN_CONFIG_SLEW_RATE = 20,
+	PIN_CONFIG_SKEW_DELAY = 21,
+	PIN_CONFIG_END = 127,	/* 0x7F */
+	PIN_CONFIG_MAX = 255, /* 0xFF */
 };
 
 #if CONFIG_IS_ENABLED(PINCTRL_GENERIC)
diff --git a/include/linux/math64.h b/include/linux/math64.h
index 08584c8f237..eaa9fd5b968 100644
--- a/include/linux/math64.h
+++ b/include/linux/math64.h
@@ -48,6 +48,9 @@ static inline u64 div64_u64(u64 dividend, u64 divisor)
 	return dividend / divisor;
 }
 
+#define DIV64_U64_ROUND_UP(ll, d)	\
+	({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); })
+
 /**
  * div64_s64 - signed 64bit divide with 64bit divisor
  */
diff --git a/include/phy.h b/include/phy.h
index c66fd43ea88..9ea4bd42db4 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -454,6 +454,32 @@ void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 				struct udevice *dev,
 				phy_interface_t interface);
+/**
+ * phy_device_create() - Create a PHY device
+ *
+ * @bus:		MII/MDIO bus that hosts the PHY
+ * @addr:		PHY address on MDIO bus
+ * @phy_id:		where to store the ID retrieved
+ * @is_c45:		Device Identifiers if is_c45
+ * @interface:		interface between the MAC and PHY
+ * @return: pointer to phy_device if a PHY is found, or NULL otherwise
+ */
+struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
+				     u32 phy_id, bool is_c45,
+				     phy_interface_t interface);
+
+/**
+ * phy_connect_phy_id() - Connect to phy device by reading PHY id
+ *			  from phy node.
+ *
+ * @bus:		MII/MDIO bus that hosts the PHY
+ * @dev:		Ethernet device to associate to the PHY
+ * @interface:		Interface between the MAC and PHY
+ * @return:		pointer to phy_device if a PHY is found,
+ *			or NULL otherwise
+ */
+struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
+				      phy_interface_t interface);
 
 static inline ofnode phy_get_ofnode(struct phy_device *phydev)
 {
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 50bf4ef3953..f577008736d 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -177,6 +177,49 @@ enum pm_query_id {
 	PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
 };
 
+enum pm_pinctrl_config_param {
+	PM_PINCTRL_CONFIG_SLEW_RATE = 0,
+	PM_PINCTRL_CONFIG_BIAS_STATUS = 1,
+	PM_PINCTRL_CONFIG_PULL_CTRL = 2,
+	PM_PINCTRL_CONFIG_SCHMITT_CMOS = 3,
+	PM_PINCTRL_CONFIG_DRIVE_STRENGTH = 4,
+	PM_PINCTRL_CONFIG_VOLTAGE_STATUS = 5,
+	PM_PINCTRL_CONFIG_TRI_STATE = 6,
+	PM_PINCTRL_CONFIG_MAX = 7,
+};
+
+enum pm_pinctrl_slew_rate {
+	PM_PINCTRL_SLEW_RATE_FAST = 0,
+	PM_PINCTRL_SLEW_RATE_SLOW = 1,
+};
+
+enum pm_pinctrl_bias_status {
+	PM_PINCTRL_BIAS_DISABLE = 0,
+	PM_PINCTRL_BIAS_ENABLE = 1,
+};
+
+enum pm_pinctrl_pull_ctrl {
+	PM_PINCTRL_BIAS_PULL_DOWN = 0,
+	PM_PINCTRL_BIAS_PULL_UP = 1,
+};
+
+enum pm_pinctrl_schmitt_cmos {
+	PM_PINCTRL_INPUT_TYPE_CMOS = 0,
+	PM_PINCTRL_INPUT_TYPE_SCHMITT = 1,
+};
+
+enum pm_pinctrl_drive_strength {
+	PM_PINCTRL_DRIVE_STRENGTH_2MA = 0,
+	PM_PINCTRL_DRIVE_STRENGTH_4MA = 1,
+	PM_PINCTRL_DRIVE_STRENGTH_8MA = 2,
+	PM_PINCTRL_DRIVE_STRENGTH_12MA = 3,
+};
+
+enum pm_pinctrl_tri_state {
+	PM_PINCTRL_TRI_STATE_DISABLE = 0,
+	PM_PINCTRL_TRI_STATE_ENABLE = 1,
+};
+
 enum zynqmp_pm_reset_action {
 	PM_RESET_ACTION_RELEASE = 0,
 	PM_RESET_ACTION_ASSERT = 1,
@@ -340,6 +383,29 @@ enum pm_ioctl_id {
 	IOCTL_GET_LAST_RESET_REASON = 23,
 	/* AIE ISR Clear */
 	IOCTL_AIE_ISR_CLEAR = 24,
+	/* Register SGI to ATF */
+	IOCTL_REGISTER_SGI = 25,
+	/* Runtime feature configuration */
+	IOCTL_SET_FEATURE_CONFIG = 26,
+	IOCTL_GET_FEATURE_CONFIG = 27,
+	/* IOCTL for Secure Read/Write Interface */
+	IOCTL_READ_REG = 28,
+	IOCTL_MASK_WRITE_REG = 29,
+	/* Dynamic SD/GEM/USB configuration */
+	IOCTL_SET_SD_CONFIG = 30,
+	IOCTL_SET_GEM_CONFIG = 31,
+	IOCTL_SET_USB_CONFIG = 32,
+	/* AIE/AIEML Operations */
+	IOCTL_AIE_OPS = 33,
+	/* IOCTL to get default/current QoS */
+	IOCTL_GET_QOS = 34,
+};
+
+enum pm_sd_config_type {
+	SD_CONFIG_EMMC_SEL = 1,	/* To set SD_EMMC_SEL in CTRL_REG_SD */
+	SD_CONFIG_BASECLK = 2,	/* To set SD_BASECLK in SD_CONFIG_REG1 */
+	SD_CONFIG_8BIT = 3,	/* To set SD_8BIT in SD_CONFIG_REG2 */
+	SD_CONFIG_FIXED = 4,	/* To set fixed config registers */
 };
 
 #define PM_SIP_SVC	0xc2000000
@@ -372,6 +438,8 @@ int zynqmp_pmufw_config_close(void);
 void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
 int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 		      u32 arg3, u32 *ret_payload);
+int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
+int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id);
 
 /* Type of Config Object */
 #define PM_CONFIG_OBJECT_TYPE_BASE	0x1U
@@ -403,5 +471,9 @@ enum zynqmp_pm_request_ack {
 #define ZYNQMP_PM_CAPABILITY_UNUSABLE	0x8U
 
 #define ZYNQMP_PM_MAX_QOS		100U
+/* Firmware feature check version mask */
+#define FIRMWARE_VERSION_MASK		GENMASK(15, 0)
+/* PM API versions */
+#define PM_API_VERSION_2		2
 
 #endif /* _ZYNQMP_FIRMWARE_H_ */