Squashed 'dts/upstream/' changes from d08867ef8f12..4d52919c55f4

4d52919c55f4 Merge tag 'v6.17-dts-raw'
38fc28fcd6fe Merge tag 'i2c-for-6.17-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
5df2896cdbcd Merge tag 'soc-fixes-6.17-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
501d5fac4d3e Merge tag 'v6.17-rockchip-dtsfixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
388d0d237317 Merge tag 'sunxi-fixes-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
9c1a1aa76d6a dt-bindings: i2c: spacemit: extend and validate all properties
f88821c169f7 Merge tag 'hid-for-linus-2025092201' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
7bb1f59ee85e Merge tag 'v6.17-rc6-dts-raw'
785f4a41a7a7 Merge tag 'phy-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
b72de0ae4a0d Merge tag 'dmaengine-fix-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
f1de2f274990 Merge tag 'tty-6.17-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
8dd5e1884a5c Merge tag 'imx-fixes-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
c0c7a4135951 Merge tag 'socfpga_dts_fix_for_v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/fixes
5f5117ff540a Merge tag 'mvebu-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes
affba3242b22 Merge commit '89c5214639294' into for-6.17/upstream-fixes
5c5133a89684 arm64: dts: marvell: cn9132-clearfog: fix multi-lane pci x2 and x4 ports
a30edc781685 arm64: dts: marvell: cn9132-clearfog: disable eMMC high-speed modes
4818551bb6d9 arm64: dts: marvell: cn913x-solidrun: fix sata ports status
e0499b5c331f ARM: dts: kirkwood: Fix sound DAI cells for OpenRD clients
b43e7c1e6d2d arm64: dts: imx8mp: Correct thermal sensor index
eaf6bab64a58 riscv: dts: allwinner: rename devterm i2c-gpio node to comply with binding
faf49552868d Merge tag 'v6.17-rc5-dts-raw'
b16ee588d71b arm64: dts: rockchip: Fix the headphone detection on the orangepi 5
e183eb884e5c arm64: dts: rockchip: Add vcc supply for SPI Flash on NanoPC-T6
d5396f16c37f ARM: dts: socfpga: sodia: Fix mdio bus probe and PHY address
ebd92f3a59b2 Merge tag 'spi-fix-v6.17-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
a526c9ef1b67 Merge tag 'soc-fixes-6.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
5d8ba326d104 Merge tag 'at91-fixes-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
509dee1b7e66 ARM: dts: microchip: sama7d65: Force SDMMC Legacy mode
9e763cb3d1b4 Merge tag 'v6.17-rockchip-dtsfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
a41fd927377f arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
18d0194799e5 dt-bindings: lpspi: Document support for S32G
c9fac75c65f2 arm64: dts: rockchip: fix USB on RADXA ROCK 5T
63ef95420b13 arm64: dts: axiado: Add missing UART aliases
b2a21e821e2c Merge tag 'imx-fixes-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
58056a8dbfc9 Merge tag 'v6.17-rc4-dts-raw'
3e7b84751e93 Merge tag 'drm-fixes-2025-08-29' of https://gitlab.freedesktop.org/drm/kernel
ea89dcf2416c Merge tag 'drm-msm-fixes-2025-08-26' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
6309b9b1efc4 arm64: dts: rockchip: Add vcc-supply to SPI flash on Pinephone Pro
e22da6a63ced Merge tag 'devicetree-fixes-for-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
f25e8f3f3e67 dt-bindings: display/msm: qcom,mdp5: drop lut clock
0b54cf7dc8d3 Merge tag 'v6.17-rc3-dts-raw'
0264ca32989f Merge tag 'mips-fixes_6.17_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
302d05793211 arm64: dts: rockchip: fix es8388 address on rk3588s-roc-pc
0704a97d3469 arm64: dts: rockchip: Fix Bluetooth interrupts flag on Neardi LBA3368
f1a75d0e9267 arm64: dts: rockchip: correct network description on Sige5
4212fbb0acb5 arm64: dts: rockchip: Minor whitespace cleanup
a52498f55fed ARM: dts: rockchip: Minor whitespace cleanup
2b74ca5ff951 arm64: dts: rockchip: Add supplies for eMMC on rk3588-orangepi-5
5135047db7f2 arm64: dts: rockchip: Fix the headphone detection on the orangepi 5 plus
510af76983ed mips: lantiq: xway: sysctrl: rename the etop node
2ff76939eff1 mips: dts: lantiq: danube: add missing burst length property
5c17501f659d ARM64: dts: mcbin: fix SATA ports on Macchiatobin
6f440931507f ARM: dts: armada-370-db: Fix stereo audio input routing on Armada 370
140d6b3980c3 arm64: dts: imx95: Fix JPEG encoder node assigned clock
c384581e7d6f arm64: dts: imx95-19x19-evk: correct the phy setting for flexcan1/2
e2edf4aaafbf arm64: dts: imx8mp: Fix missing microSD slot vqmmc on Data Modul i.MX8M Plus eDM SBC
4ea5d96804b4 arm64: dts: imx8mp: Fix missing microSD slot vqmmc on DH electronics i.MX8M Plus DHCOM
2789604fc218 arm64: dts: imx8mp-tqma8mpql: remove virtual 3.3V regulator
a573a81d351e arm64: dts: imx8mp-tqma8mpql: fix LDO5 power off
e96897446ad9 Merge tag 'regulator-fix-v6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
694d45a2f761 dt-bindings: vendor-prefixes: add eswin
f16c7cbc671f ARM: dts: allwinner: Minor whitespace cleanup
9e29f1c5986c Merge tag 'v6.17-rc2-dts-raw'
43c415b40654 Merge tag 'net-6.17-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
e24d016dedd9 dt-bindings: serial: 8250: allow "main" and "uart" as clock names
93772d487e42 dt-bindings: serial: 8250: move a constraint
fa1b88e6663a dt-bindings: serial: brcm,bcm7271-uart: Constrain clocks
4982fdb2c306 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings
23a1689d9a68 dt-bindings: phy: marvell,comphy-cp110: Fix clock and child node constraints
d57c7d5cb3fe riscv: dts: thead: Add APB clocks for TH1520 GMACs
32097674787b dt-bindings: net: thead,th1520-gmac: Describe APB interface clock
25370078d056 regulator: dt-bindings: infineon,ir38060: Add Guenter as maintainer from IBM
5b650c7a3387 Merge tag 'v6.17-rc1-dts-raw'
f579ec5f89fe arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3399-pinebook-pro
401adf630a1b arm64: dts: rockchip: mark eeprom as read-only for Radxa E52C
f6fe1e119a05 dt-bindings: dma: qcom: bam-dma: Add missing required properties
6eb6301028f5 Merge tag 'mailbox-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
7beab77fbc66 Merge tag 'soc-fixes-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
9c15d4d232b9 Merge tag 'tegra-for-6.17-arm64-dt-v3' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes
d818fcb1ce10 Merge tag 'net-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
c669bebbe274 Merge tag 'loongarch-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
d25371e88f49 Merge tag 'input-for-v6.17-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
b225444b125e dt-bindings: mailbox: Add ASPEED AST2700 series SoC
4022f68499d8 dt-bindings: mailbox: Drop consumers example DTS
08a32727c5e5 dt-bindings: mailbox: nvidia,tegra186-hsp: Use generic node name
3ed8929022ea dt-bindings: mailbox: Correct example indentation
08534e6d0a28 dt-bindings: mailbox: ti,secure-proxy: Add missing reg maxItems
c26f859e6afe dt-bindings: mailbox: amlogic,meson-gxbb-mhu: Add missing interrupts maxItems
a98189806d7f dt-bindings: mailbox: qcom-ipcc: document the Milos Inter-Processor Communication Controller
bcdf210f6039 dt-bindings: mailbox: Add support for bcm74110
7861e592add4 Merge branch 'next' into for-linus
e6595131966d Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
a317294a0141 dt-bindings: net: Replace bouncing Alexandru Tachici emails
9177d7f279b3 Input: add keycode for performance mode key
5bd774b49823 LoongArch: dts: Add eMMC/SDIO controller support to Loongson-2K2000
d2b50965e07c LoongArch: dts: Add SDIO controller support to Loongson-2K1000
20c7a872f5fd LoongArch: dts: Add SDIO controller support to Loongson-2K0500
65a3167b6e72 Merge tag 'i2c-for-6.17-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
8deaba69701b Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
5927e9980011 Merge tag 'rtc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
9b82ded0a5a8 Merge tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux
74cfe0883b3c Merge tag 'i2c-host-6.17-pt2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
a29a05ff2d8d Merge tag 'pinctrl-v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
f43f3f8a2149 Merge tag 'rproc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
06484243d8ee Merge tag 'pci-v6.17-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
38d94dc8574d Merge tag 'linux-watchdog-6.17-rc1' of git://www.linux-watchdog.org/linux-watchdog
81e6b5eb1307 Merge tag 'dmaengine-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
912ad91d462a Merge tag 'phy-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
fc1b311a55ee Merge tag 'sound-6.17-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
f898700a53a9 Merge tag 'for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
19d393592c86 Merge branch 'pci/controller/sophgo'
522b974af253 Merge branch 'pci/controller/qcom'
b6336c96a490 Merge branch 'pci/controller/brcmstb'
eaddf7ef5e04 dt-bindings: PCI: qcom,pcie-sa8775p: Document 'link_down' reset
b61473b60b3f dt-bindings: PCI: Remove 83xx-512x-pci.txt
95e7dfd2b09c dt-bindings: PCI: Convert amazon,al-alpine-v[23]-pcie to DT schema
d855db32b1d6 dt-bindings: PCI: Convert marvell,armada-3700-pcie to DT schema
faa8038a538e dt-bindings: PCI: Convert apm,xgene-pcie to DT schema
b64147052a31 dt-bindings: PCI: Convert axis,artpec6-pcie to DT schema
89b27dfc989f dt-bindings: PCI: Convert st,spear1340-pcie to DT schema
761305253c7f Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
7f4c60d44458 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
d2166900176e Merge tag 'hwmon-for-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
f654a4cffc8e Merge tag 'media/v6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
c68e5f5d8510 Merge tag 'leds-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
5fa7da3742d2 Merge tag 'mfd-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
d48c5718d931 Merge tag 'gnss-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss
f19dc807ef82 Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
88ef88367045 Merge tag 'nand/for-6.17' into mtd/next
77ce7c807f31 Merge tag 'spi-nor/for-6.17' into mtd/next
617063dc7992 Merge tag 'v6.17-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
fb35ad6772e3 arm64: tegra: Remove numa-node-id properties
5d5d47c2898d Merge branch 'clk-fixes' into clk-next
1810b29ee894 Merge tag 'drm-next-2025-07-30' of https://gitlab.freedesktop.org/drm/kernel
672251f07f5f Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
1c4c35171c77 dt-bindings: i3c: Add Renesas I3C controller
acc6ad02daf0 Merge tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux
913a827d8026 Merge tag 'arm-soc/for-6.16/devicetree-fixes' of https://github.com/Broadcom/stblinux into for-next
ce735da13c91 Merge tag 'net-next-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
23ad1dd8a0f2 mfd: dt-bindings: Convert TPS65910 to DT schema
ebcd01abab45 Merge tag 'powerpc-6.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
fabc9eb3b96b dt-bindings: i2c: apple,i2c: Document Apple A7-A11, T2 compatibles
f08139dcfa69 Merge branches 'clk-rockchip', 'clk-thead', 'clk-microchip', 'clk-imx' and 'clk-qcom' into clk-next
fe77e800d26c Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next
f9a15ab8af76 Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
84946f9433bb Merge tag 'irq-drivers-2025-07-27' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
11f0d2c420f3 Merge tag 'mmc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc
7dff1db3c967 Merge tag 'pmdomain-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
7a67b758e4c6 Merge tag 'i2c-for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
059f314983b4 Merge tag 'soc-newsoc-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
935ca70fe88a Merge tag 'soc-drivers-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f210f652efaa Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
33c1d430f189 Merge tag 'devicetree-for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
ca819c3ba978 Merge tag 'usb-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
86157d6ef538 Merge tag 'tty-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
638f234e9940 Merge tag 'char-misc-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
206f073acf2c Merge tag 'kvmarm-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
f1208bcf4c31 Merge tag 'pwm/for-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
60c278df97a4 Merge tag 'spi-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
06e9819c6572 Merge tag 'regulator-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
6094cd275fea Merge tag 'gpio-updates-for-v6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
fe3cebf87ff8 Merge tag 'sound-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
ccd9a5c60b97 Merge tag 'thermal-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
1ed339a1dd9b Merge tag 'pm-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
dbfbda98c7fa dt-bindings: Correct indentation and style in DTS example
1c1a12439958 MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller
2d80b8cff673 dt-bindings: hwmon: Replace bouncing Alexandru Tachici emails
a9536c4a533e dt-bindings: Add INA228 to ina2xx devicetree bindings
ba8204028427 dt-bindings: input: touchscreen: st1232: add touch-overlay example
1633cb20b256 dt-bindings: touchscreen: add touch-overlay property
06b06ef8f47d Input: Add and document BTN_GRIP*
59ae00fd8e64 dt-bindings: input: syna,rmi4: Document F1A function
cc47e10c64b0 dt-bindings: ieee802154: Convert at86rf230.txt yaml format
b966613384a2 Merge tag 'sunxi-fixes-for-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
3849b529499b dt-bindings: net: dsa: microchip: Add KSZ8463 switch support
6979cbfbf41e dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5
6b627bb260fd Merge tag 'qcom-drivers-for-6.17-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
233d517c1884 dt-bindings: i2c: i2c-rk3x: Allow use of a power-domain
7049499f9e5a dt-bindings: i2c: exynos5: add samsung,exynos2200-hsi2c compatible
fc7ae9ba5fb2 dt-bindings: net: dsa: b53: Document brcm,gpio-ctrl property
3c4710ce3e81 dt-bindings: display: mediatek,dp: Allow DisplayPort AUX bus
646525defa14 dt-bindings: fsl: convert fsl,vf610-mscm-ir.txt to yaml format
137ad9b12805 dt-bindings: interrupt-controller: Add fsl,icoll.yaml
648b651777b1 dt-bindings: interrupt-controller: Add missing Xilinx INTC binding
b41b883df97c scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
8523d45b2495 scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes
3f060c24c171 scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host
711056c3ae41 Merge tag 'for-net-next-2025-07-23' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next
dd1b4057dd88 Merge tag 'wireless-next-2025-07-24' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
155dc9a613a6 spi: sophgo: Add SPI NOR controller for SG2042
bb7c1194a99d Add RSPI support for RZ/V2H
50fd75a061ed dt-bindings: clock: convert lpc1850-cgu.txt to yaml format
24140d806f08 dt-bindings: clock: Convert qca,ath79-pll to DT schema
6e04ef32ef38 dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema
2db6f9a1da8f dt-bindings: clock: Convert moxa,moxart-clock to DT schema
001cac37e6e6 dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema
0cd4ab636909 dt-bindings: clock: Convert maxim,max9485 to DT schema
1c33570f5d22 support for amlogic the new SPI IP
a14fec537070 dt-bindings: clock: Convert qcom,krait-cc to DT schema
fa19909f10d5 dt-bindings: clock: qcom: Remove double colon from description
b039af46152a Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
a162ca77489e spi: dt-bindings: Document the RZ/V2H(P) RSPI
3d1aedbd9343 ASoC: dt-bindings: atmel,at91-ssc: add microchip,sam9x7-ssc
0bdf06c97664 spi: dt-bindings: Add binding document of Amlogic SPISG controller
4e1353cbd1b1 spi: dt-bindings: spi-sg2044-nor: Change SOPHGO SG2042
9707aa6ab611 Merge tag 'ib-mfd-gpio-power-soc-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
8ee72356e984 dt-bindings: mfd: rk806: Allow to customize PMIC reset mode
28d9430f0964 dt-bindings: mfd: samsung,s2mps11: Add comment about interrupts properties
4563fdbc72d2 dt-bindings: mfd: fsl,imx8qxp-csr: Remove binding documentation
8f9f74c9d030 dt-bindings: mfd: Convert lpc1850-creg-clk, pc1850-dmamux and phy-lpc18xx-usb-otg to YAML format
75a11ccc6567 dt-bindings: mfd: convert mxs-lradc bindings to json-schema
8978eadc5578 Merge branches 'ib-mfd-gpio-input-pwm-6.17', 'ib-mfd-gpio-power-soc-6.17' and 'ib-mfd-misc-pinctrl-6.17' into ibs-for-mfd-merged
4e0a772975ea dt-bindings: gpio: rockchip: Allow use of a power-domain
f5cd2bf1e8fb dt-bindings: serial: snps-dw-apb-uart: Allow use of a power-domain
5d324bdff50d dt-bindings: serial: samsung: add samsung,exynos2200-uart compatible
0a9a83ae140d dt-bindings: mfd: Add Apple Mac System Management Controller
c7fa9a3843ab dt-bindings: power: reboot: Add Apple Mac SMC Reboot Controller
f4eddbec1946 dt-bindings: gpio: Add Apple Mac SMC GPIO block
09c00fdd331c Merge tag 'icc-6.17-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
ff8150e0b0f2 dt-bindings: i2c: nxp,pnx-i2c: allow clocks property
83fafeb193c6 dt-bindings: i2c: renesas,riic: Document RZ/T2H and RZ/N2H support
bd1edaf90e4d dt-bindings: i2c: renesas,riic: Move ref for i2c-controller.yaml to the end
4fb79a323ffa dt-bindings: rtc: amlogic,a4-rtc: Add compatible string for C3
6911acf4bf27 Merge tag 'riscv-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
d6c5bd06ba88 Merge tag 'samsung-drivers-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
5335c6dec4f1 Merge tag 'arm-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/newsoc
36beceecc031 Merge tag 'riscv-sophgo-dt-for-v6.17' of https://github.com/sophgo/linux into soc/dt
a94a0024593d dt-bindings: rtc: pcf85063: add binding for RV8063
355ece2bba05 dt-bindings: net: bluetooth: nxp: add support for supply and reset
c94c0ee603b8 dt-bindings: net: bluetooth: nxp: Add support for 4M baudrate
da422e2fd590 ASoC: dt-bindings: qcom,sm8250: Add Fairphone 4 sound card
d443d69fe59a ASoC: dt-bindings: qcom,q6afe: Document q6usb subnode
e1dc5fef731a dt-bindings: dma: fsl-mxs-dma: allow interrupt-names for fsl,imx23-dma-apbx
831ba7ce88cf dt-bindings: dma: Convert marvell,orion-xor to DT schema
d809488a383f dt-bindings: dma: Convert brcm,iproc-sba to DT schema
102be241c4b4 dt-bindings: dma: qcom,gpi: document the Milos GPI DMA Engine
57e8d0f51565 dt-bindings: pinctrl: mediatek: Add support for mt8189
143c71ae555f dt-bindings: net: wireless: rt2800: add SOC Wifi
3b69bcbd0f88 MIPS: dts: ralink: mt7620a: add wifi
b2e237f8d950 dt-bindings: power: rpmpd: Add Glymur power domains
ecb488880deb dt-bindings: leds: ncp5623: Add 0x39 as a valid I2C address
a4e266b64b63 dt-bindings: display: sprd,sharkl3-dsi-host: Fix missing clocks constraints
a4902ad760ba dt-bindings: display: sprd,sharkl3-dpu: Fix missing clocks constraints
9871ccfc7c82 dt-bindings: display: imx: convert fsl,dcu.txt to yaml format
cb3eab704df6 dt-bindings: timer: via,vt8500-timer: Convert to YAML
02bc5b47191f dt-bindings: net: Convert Marvell Armada NETA and BM to DT schema
d2cb17b16fcd arm64: dts: sophgo: Add Duo Module 01 Evaluation Board
e9a69b5764c5 arm64: dts: sophgo: Add Duo Module 01
d46c534cd1a4 arm64: dts: sophgo: Add initial SG2000 SoC device tree
ecee37b0c732 riscv: dts: sophgo: fix mdio node name for CV180X
edeb5fb8a57f riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
39cea134a435 riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
3af1443caa87 riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
d95438e9cc23 dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
97ff3450b45b riscv: dts: sophgo: add ethernet GMAC device for sg2042
6523097f467e riscv: dts: sophgo: Enable ethernet device for Huashan Pi
9d7ba84277ac riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
5ad41c12bb04 riscv: dts: sophgo: Add ethernet device for cv18xx
9c62ec1b061f riscv: dts: sophgo: sg2044: add pmu configuration
e204a42647dc riscv: dts: sophgo: sg2044: add ziccrse extension
e64ca04dfa1a riscv: dts: sophgo: add zfh for sg2042
af70f42b8563 riscv: dts: sophgo: add ziccrse for sg2042
341c9d72df4f riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
867de304b18d riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
084dbab95812 riscv: dts: sophgo: sg2044: add MSI device support for SG2044
f3f305412cd9 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
d4c78bf20a68 riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
ca25c70f2e20 dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
b116c2ce6c9e riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
a7465701ba1b riscv: dts: sophgo: add pwm controller for SG2044
2d4c469f3e0c riscv: dts: sophgo: add SG2044 SPI NOR controller driver
6ed1d5df4964 riscv: dts: sophgo: sg2044: Add pinctrl device
0e92ebbc7780 riscv: dts: sophgo: sg2044: Add ethernet control device
f20278d13b83 riscv: dts: sophgo: sophgo-srd3-10: add HWMON MCU device
1ab417f2c6d5 riscv: dts: sophgo: sg2044: Add MMC controller device
5234c1aec3a0 riscv: dts: sophgo: sg2044: add DMA controller device
72423eef988d riscv: dts: sophgo: sg2044: Add I2C device
a82a340b1d6b riscv: dts: sophgo: sg2044: Add GPIO device
733f28e2c1dc riscv: dts: sophgo: sg2044: Add clock controller device
8fa3d034a693 riscv: dts: sophgo: sg2044: Add system controller device
0adb6607aa87 riscv: dts: sophgo: cv18xx: Add RTCSYS device node
551dd312e065 Merge tag 'apple-soc-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
0c7b9e2e286d Merge tag 'at91-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
bd42c1ae49a9 Merge tag 'thead-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
773cec14b76e Merge tag 'v6.17-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
6daf8e447699 ARM: dts: st: spear: Use generic "ethernet" as node name
515a597ed8c8 Merge tag 'qcom-drivers-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
a7a24115ee9b Merge tag 'memory-controller-drv-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
3c035ea894fb dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible
564f3f7a8a9d Merge tag 'tegra-for-6.17-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers
90505e583326 Merge branch 'newsoc/axiado' into soc/newsoc
d2c0ccccbebb arm64: dts: axiado: Add initial support for AX3000 SoC and eval board
676074106b8d dt-bindings: i3c: cdns: add Axiado AX3000 I3C controller
6ac4d3ce41ab dt-bindings: serial: cdns: add Axiado AX3000 UART controller
007d178e28db dt-bindings: gpio: cdns: add Axiado AX3000 GPIO variant
c2b4468d9adc dt-bindings: gpio: cdns: convert to YAML
5a5a1053ea3b dt-bindings: arm: axiado: add AX3000 EVK compatible strings
10f07517af93 dt-bindings: vendor-prefixes: Add Axiado Corporation
5583ebf434fb Merge tag 'mvebu-dt-6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
502759c762d2 Merge tag 'amlogic-arm64-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
c839bab293d1 Merge tag 'qcom-arm64-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
3fccb04b054a Merge tag 'sunxi-dt-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
5507affeb4ce Merge tag 'ti-k3-dt-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
0390f8569044 Merge tag 'qcom-arm32-for-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
82b6193bcad3 Merge tag 'spacemit-dt-for-6.17-1' of https://github.com/spacemit-com/linux into soc/dt
048993d6cfca Merge tag 'imx-bindings-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
16c8d6c0186c Merge tag 'imx-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
200442757655 Merge tag 'imx-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
5dbe4280d749 Merge tag 'socfpga_dts_updates_for_v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
df2b1b31d3ab Merge tag 'tegra-for-6.17-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
92326a333c76 Merge tag 'tegra-for-6.17-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
2e35e6c04a0e Merge tag 'tegra-for-6.17-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
0b4b59ce9c57 dt-bindings: qcom: geni-se: describe SA8255p
32ebdce75966 dt-bindings: serial: describe SA8255p
c5b78d58092e Merge branches 'pm-misc' and 'pm-tools'
cb4c9d49e8ae dt-bindings: phy: Convert brcm,sr-usb-combo-phy to DT schema
b71d5d92eed1 dt-bindings: phy: Convert ti,da830-usb-phy to DT schema
7113f012a446 dt-bindings: phy: marvell,mmp2-usb-phy: Drop status from the example
b8380346183a dt-bindings: phy: mixel, mipi-dsi-phy: Allow assigned-clock* properties
bc9f6c56ebf6 dt-bindings: phy: qcom,snps-eusb2: document the Milos Synopsys eUSB2 PHY
e8bf211ef002 dt-bindings: usb: qcom,snps-dwc3: Add Milos compatible
b1b5a102a159 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings for QCS615
4793916c4605 Merge branch 'icc-milos' into icc-next
ca79b1e41699 Merge tag 'ath-next-20250721' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath into wireless-next
4a7813db0edd dt-bindings: thermal: tegra: Document Tegra210B01
647d14815aa7 dt-bindings: thermal: mediatek: Add fallback compatible string for MT7981 and MT8516
8cbb6e090113 dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
c75e65fa1a7a dt-bindings: serial: 8250: spacemit: set clocks property as required
3d801ddabd51 dt-bindings: serial: renesas: Document RZ/V2N SCIF
8004034be86b arm64: dts: apple: Add Apple SoC GPU
372bb0a9270c dt-bindings: gpu: Add Apple SoC GPU
0fd845e2039f arm64: dts: apple: t8012-j132: Include touchbar framebuffer node
def9acb229f9 arm64: dts: apple: Add bit offset to PMIC NVMEM node names
dc4bff407bcd Merge branch 'newsoc/cix-p1' into soc/newsoc
c9853b29c44c arm64: dts: cix: Add sky1 base dts initial support
566f7b29d383 dt-bindings: clock: cix: Add CIX sky1 scmi clock id
2d860dd2a924 dt-bindings: mailbox: add cix,sky1-mbox
4c129f674cb4 dt-bindings: arm: add CIX P1 (SKY1) SoC
ec61ee7dfba5 dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
7ebb5edbb224 Merge branch 'newsoc/andes' into soc/newsoc
629e67c23eef Merge tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
d845a9c7f436 Merge tag 'mtk-dts32-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
8b47485f6798 Merge tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
866ff7150b56 Merge tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
ea5f4eb45cdb Merge tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
09a326b741de arm64: dts: nuvoton: npcm8xx: Drop the GIC "ppi-partitions" node
ca6ab3278201 Merge tag 'aspeed-6.17-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
12f66471cea2 Merge tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
ce29d48849d5 Merge tag 'renesas-dt-bindings-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
d5a3aec241ba Merge tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
61ffff1eadc1 Merge tag 'samsung-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
c241df52dbd4 Merge tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
5a97ca254d34 Merge tag 'arm-soc/for-6.17/drivers' of https://github.com/Broadcom/stblinux into soc/drivers
615e5dd1026f Merge tag 'v6.16-rc7' into tty-next
bfb15af09263 riscv: dts: andes: add Voyager board device tree
e75c75ca51e1 riscv: dts: andes: add QiLai SoC device tree
40e05487b65c dt-bindings: timer: add Andes machine timer
96e291cff48a dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
5a070b8aab00 dt-bindings: interrupt-controller: add Andes QiLai PLIC
23b07e5175ad dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
6f6f2755eb71 Merge tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux into soc/drivers
d0eccdbd78de spidev: introduce trivial abb sensor device
e899273b9ee5 dt-bindings: trivial-devices: Document ABB sensors
39715dac45f4 PM: docs: Use my kernel.org address in ABI docs and DT bindings
9f70470351fe Merge tag 'v6.16-rc7' into usb-next
4d4776db387d dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
9a7abe6a0109 dt-bindings: hwmon: adt7475: Allow and recommend #pwm-cells = <3>
8e0e30e58cfa dt-bindings: trivial: Add tps53685 support
0ba69b597265 dt-bindings: hwmon: pmbus/adp1050: Add adp1051, adp1055 and ltp8800
5538f47fb83b dt-bindings: hwmon: pmbus: ti,ucd90320: Add missing compatibles
70a810c569f2 dt-bindings: hwmon: maxim,max20730: Add maxim,max20710 compatible
684ed1fcb89b dt-bindings: hwmon: lltc,ltc2978: Add lltc,ltc713 compatible
ceb2f4ae7231 dt-bindings: hwmon: ti,lm87: Add adi,adm1024 compatible
6fda8eb1d30f dt-bindings: hwmon: national,lm90: Add missing Dallas max6654 and onsemi nct72, nct214, and nct218
fec5aa716025 dt-bindings: hwmon: amc6821: Add cooling levels
2a3bb1bc029e dt-bindings: hwmon: (pmbus/isl68137) Add RAA229621 support
df9399258d45 dt-bindings: clock: qcom,sm4450-dispcc: Reference qcom,gcc.yaml
a21d5e131452 dt-bindings: clock: qcom,sm4450-camcc: Reference qcom,gcc.yaml
c26aa209d9af dt-bindings: clock: qcom,mmcc: Reference qcom,gcc.yaml
101385caa206 dt-bindings: clock: qcom,sm8150-camcc: Reference qcom,gcc.yaml
bf0ad3272a8d dt-bindings: clock: qcom: Remove double colon from description
5e0de7d92ba1 Merge tag 'iio-for-6.17a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
ed2c0a3539b9 dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio'
16222f5add7f dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC
26e8a1a26a63 dt-bindings: interconnect: qcom: Remove double colon from description
f3990f2988aa dt-bindings: gpio: Convert qca,ar7100-gpio to DT schema
f4169e8902ba dt-bindings: gpio: Convert maxim,max3191x to DT schema
cc96527c4361 dt-bindings: gpio: fsl,qoriq-gpio: Add missing mpc8xxx compatibles
234beb04554a dt-bindings: gpio: Create a trivial GPIO schema
d5b6bbdd5ea6 dt-bindings: gpio: Convert st,spear-spics-gpio to DT schema
57d91fffc5cb dt-bindings: gpio: Convert abilis,tb10x-gpio to DT schema
baf1be13c404 dt-bindings: gpio: Convert apm,xgene-gpio-sb to DT schema
bb01ffde4219 dt-bindings: gpio: Convert ti,twl4030-gpio to DT schema
7c869e945c1d dt-bindings: gpio: Convert lantiq,gpio-mm-lantiq to DT schema
2d351d673ed0 dt-bindings: gpio: Convert ti,keystone-dsp-gpio to DT schema
d1caee930967 dt-bindings: gpio: Convert altr,pio-1.0 to DT schema
f6b6f6538c88 dt-bindings: gpio: Convert cirrus,clps711x-mctrl-gpio to DT schema
f5b06d065b65 dt-bindings: gpio: Convert cavium,octeon-3860-gpio to DT schema
6ebb1a828301 dt-bindings: gpio: Convert exar,xra1403 to DT schema
2785b36e35cc dt-bindings: gpio: Convert microchip,pic32mzda-gpio to DT schema
b56e20fc40d7 dt-bindings: gpio: Convert lacie,netxbig-gpio-ext to DT schema
3ccc1ca7e0ba Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
8f379560c370 dt-bindings: trivial-devices: Add undocumented hwmon devices
39de5984956e dt-bindings: arm-smmu: Remove sdm845-cheza specific entry
a1ac450f3634 arm64: dts: rockchip: Add maskrom button to NanoPi R5S + R5C
af0325e129ae dt-bindings: thermal: qcom-tsens: document the Milos Temperature Sensor
49cc1296037b dt-bindings: clock: qcom: document the Milos Video Clock Controller
16340601924b dt-bindings: clock: qcom: document the Milos GPU Clock Controller
573f59c35a7e dt-bindings: clock: qcom: document the Milos Display Clock Controller
da3d8ec933a1 dt-bindings: clock: qcom: document the Milos Camera Clock Controller
108d90ed45b5 dt-bindings: clock: qcom: document the Milos Global Clock Controller
b1a99cb677d8 dt-bindings: clock: qcom,x1e80100-gcc: Add missing video resets
9e4ffed3ade8 dt-bindings: clock: qcom,sm8450-videocc: Document X1E80100 compatible
741514539768 dt-bindings: clock: qcom: document the Milos TCSR Clock Controller
97ec633f5480 dt-bindings: clock: qcom: Document the Milos RPMH Clock Controller
6d406a229797 dt-bindings: clock: Add Qualcomm QCS615 Video clock controller
8b50d3c9c410 dt-bindings: clock: Add Qualcomm QCS615 Graphics clock controller
d0090474f382 dt-bindings: clock: Add Qualcomm QCS615 Display clock controller
942ecba2c8f9 dt-bindings: clock: Add Qualcomm QCS615 Camera clock controller
82a322763a4f Merge branch '20250516-ipq5018-cmn-pll-v4-2-389a6b30e504@outlook.com' into clk-for-6.17
9eefab0dfdd5 dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC
a1b9cfc98bd3 dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible
d5da90eccdff dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel
34786aba9ba7 dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface
6e113c99e893 dt-bindings: arm: qcom,ids: Add SoC IDs for SM7635 family
fd8cea27d9ae dt-bindings: net: cdns,macb: Add external REFCLK property
aec48256a2ff dt-bindings: thermal: rockchip: document otp thermal trim
328772974a15 dt-bindings: rockchip-thermal: Add RK3576 compatible
19f989a5bd1d MIPS: mobileye: eyeq5: add two GPIO bank nodes
6b4ac8add716 MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor
4fd343c406b0 MIPS: mobileye: eyeq5: add 5 I2C controller nodes
e68a2aba902d dt-bindings: watchdog: nxp,pnx4008-wdt: allow clocks property
9c8255dc203b riscv: dts: starfive: jh7110-common: add status power led node
22723d632890 riscv: dts: starfive: jh7110-milkv-mars sort properties
e455f730d5b8 dt-bindings: nvmem: convert vf610-ocotp.txt to yaml format
5e169c37d95c dt-bindings: nvmem: mediatek: efuse: split MT8186/MT8188 from base version
7a10c41bf9e8 dt-bindings: nvmem: SID: Add binding for A523 SID controller
cbc42a476e75 dt-bindings: nvmem: convert lpc1857-eeprom.txt to yaml format
abc73f36bf9d dt-bindings: nvmem: fixed-layout: Allow optional bit positions
813b29da2d55 ASoC: dt-bindings: qcom,lpass-va-macro: Define clock-names in top-level
c33c7fb45109 dt-bindings: display: Add Sitronix ST7567 LCD Controller
c9198fbc442e dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
8cd3784e53b6 spi: dt-bindings: spi-mux: Drop "spi-max-frequency" as required
a08ba8cf59b0 dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node
8ab2a8849856 dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex
e7eea35f2725 arm64: dts: rockchip: Drop regulator-compatible property on rk3399
1fd0e3d44d5a arm64: dts: rockchip: Drop unneeded address+size-cells on px30
43cbc3eb401a arm64: dts: rockchip: Fix LCD panel port on rk3566-pinetab2
d654d06cfa41 arm64: dts: rockchip: Move mipi_out node on rk3399 haikou demo dtso
2e4252d482d0 arm64: dts: rockchip: Simplify mipi_out endpoint on rk3399 RP64 dtso
34b2c6e27343 arm64: dts: rockchip: Simplify edp endpoints on several rk3399 boards
c824fe70648a arm64: dts: rockchip: Simplify VOP port definition on rk3328
fa7552a02970 dt-bindings: usb: convert lpc32xx-udc.txt to yaml format
c80a7e0d3ea3 ARM: dts: broadcom: Fix bcm7445 memory controller compatible
1ef58d48a6ef dt-bindings: display: panel: samsung,atna30dw01: document ATNA30DW01
e77e4c64d3aa arm64: dts: allwinner: a523: enable Mali GPU for all boards
bf3f984838fb arm64: dts: allwinner: a523: add Mali GPU node
497e5ea363fe arm64: dts: allwinner: a523: Add power controller device nodes
9467e9442c85 Merge branch 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm into sunxi/dt-for-6.17
cc2d2d0d56f2 dt-bindings: mmc: sdhci-msm: document the Milos SDHCI Controller
b028e9e71dbc dt-bindings: power: Add A523 PPU and PCK600 power controllers
a266236fefcb arm64: dts: rockchip: Move dsi address+size-cells from SoC to rk3399 boards
ab7cf99a1f4a arm64: dts: rockchip: Move dsi address+size-cells from SoC to px30 boards
f8d95046048f dt-bindings: display: rockchip,dw-mipi-dsi: Drop address/size cells
597bb0d8411a dt-bindings: arm-smmu: document the support on Milos
ee596924f1a1 arm64: dts: rockchip: Fix UART DMA support for RK3528
01647aa1b636 arm64: dts: rockchip: Add reset button to NanoPi R5S
a74d4de252fd arm64: dts: rockchip: Add rtc0 alias for NanoPi R5S + R5C
46a8ca674cfa dt-bindings: interrupt-controller: Convert apm,xgene1-msi to DT schema
e07aac30910c dt-bindings: gpu: mali-bifrost: Add Allwinner A523 compatible
609204d3eec9 docs: dt: writing-schema: Document preferred order of properties
91dffad70433 docs: dt: writing-bindings: Document discouraged instance IDs
7d0a75ec87a1 docs: dt: writing-bindings: Document compatible and filename naming
ce2424aea4e8 docs: dt: submitting-patches: Avoid 'YAML' in the subject and add an example
cfcbcd138f50 dt-bindings: iio: proximity: Add Nicera D3-323-AA PIR sensor
1dc1537a1cfc dt-bindings: vendor-prefixes: Add Nicera
50d9d6206314 dt-bindings: iio: adc: Add support for MT7981
e3979d4e5a71 dt-bindings: iio: adc: Add AD4170-4
d56febcf05e4 dt-bindings: pinctrl: stm32: Introduce HDP
fad75c97710c Add RPMh regulator support for PM7550 & PMR735B
02ea21d540c3 ASoC: codec: Convert to GPIO descriptors for
89d0b8fce36f regulator: dt-bindings: qcom,rpmh: Add PMR735B compatible
c8bd9fcae9a0 regulator: dt-bindings: qcom,rpmh: Add PM7550 compatible
d4e6b1fb0783 dt-bindings: iio: adc: mt6359: Add MT6373 PMIC AuxADC
098202eec4e1 dt-bindings: iio: adc: mt6359: Add MT6363 PMIC AuxADC
1697eb314369 arm64: dts: imx8q: add camera ov5640 support for imx8qm-mek and imx8qxp-mek
28dbe992a899 arm64: dts: altera: socfpga_stratix10: update internal oscillators
df7e566fd9d3 arm64: dts: socfpga: swvp: remove phy-addr in the GMAC node
58018d66ed16 arm64: dts: socfpga: swvp: remove cpu1-start-addr
ed76c055b420 arm64: dts: socfpga: swvp: remove altr,modrst-offset
aec88103429c arm64: dts: socfpga: stratix10: fix dtbs_check for rstmgr
39d9a2cbc5e5 arm64: dts: socfpga: agilex: fix dtbs_check warning for f2s-free-clk
ef70c327c3f6 arm64: dts: allwinner: A523: Add SID controller node
752c7e4e2720 arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support
fae71aaf339e arm64: dts: allwinner: a100: Add EMAC support
b38274d492ca arm64: dts: allwinner: a100: Add pin definitions for RGMII/RMII
ed798b2f7978 media: dt-bindings: rockchip: Add RK3576 Video Decoder bindings
8a915333fc1e media: dt-bindings: rockchip: Document RK3588 Video Decoder bindings
9b65179d600c dt-bindings: pinctrl: document the Milos Top Level Mode Multiplexer
fb32a87d3875 dt-bindings: pinctrl: qcom,pmic-gpio: Add PM7550 support
9391657b90c6 dt-bindings: pinctrl: qcom,pmic-gpio: Add PMIV0104 support
d655238fffbd ARM: tegra: chagall: Add embedded controller node
8f97653e1318 ARM: tegra: Add device-tree for Asus Portable AiO P1801-T
800285ab20bb dt-bindings: arm: tegra: Add Asus Portable AiO P1801-T
2a2952b67a2e arm64: tegra: Add p3971-0089+p3834-0008 support
ce7e69af42ca arm64: tegra: Add memory controller on Tegra264
a81e86db62db arm64: tegra: Add Tegra264 support
a6689e2bd732 dt-bindings: arm: tegra: Add Asus VivoTab RT TF600T
776d06cf806e dt-bindings: Add Tegra264 clock and reset definitions
536f700e61e8 dt-bindings: tegra: Document P3971-0089+P3834-0008 Platform
c9998640b0fc dt-bindings: rtc: tegra: Document Tegra264 RTC
9aacfd76da1d dt-bindings: dma: Add Tegra264 compatible string
7def90ff5f38 dt-bindings: misc: Document Tegra264 APBMISC compatible
a59edbcea209 dt-bindings: firmware: Document Tegra264 BPMP
26008a3fa73f dt-bindings: mailbox: tegra-hsp: Properly sort compatible string list
ac67362457ac dt-bindings: mailbox: tegra-hsp: Bump number of shared interrupts
88181419846e dt-bindings: memory: tegra: Add Tegra264 support
80cb84e4d5a7 dt-bindings: tegra: pmc: Add Tegra264 compatible
44788ad15192 arm64: dts: rockchip: describe the OV8858 user camera on PinePhone Pro
f48d16bc01ed arm64: dts: rockchip: describe I2c Bus 1 and IMX258 world camera on PinePhone Pro
624791f8d74a arm64: dts: rockchip: Fix pinctrl node names for RK3528
2a7b4ab8ef90 arm64: dts: rockchip: Add FriendlyElec NanoPi M5 support
75ac9bbd660a dt-bindings: arm: rockchip: add FriendlyElec NanoPi M5 board
d9c568906be1 arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger
8bd14566b75f arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar
0e417bfcbc38 arm64: dts: rockchip: add header for RK8XX PMIC constants
5cdc97a0faf8 arm64: dts: rockchip: add HDMI audio on ROCK 4D
d2defdc9b0c3 arm64: dts: rockchip: theoretically enable Wi-Fi on ROCK 4D
7200ec33cb56 arm64: dts: rockchip: complete USB nodes on ROCK 4D
ac5675c9dfae arm64: dts: rockchip: adjust dcin regulator on ROCK 4D
71bbd4df5a38 arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
c3eb8bf27be6 dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
3dbe8d040691 dt-bindings: mmc: sdhci-pxa: restrict pinctrl to pxav1
256a25acb085 arm64: dts: freescale: imx8mp-toradex-smarc: remove gpio hog
4875356dd0d1 arm64: dts: freescale: imx8mp-toradex-smarc: fix lvds dsi mux gpio
7e16a47c774f arm64: dts: imx8mm-venice-gw7904: Increase HS400 USDHC clock speed
958eae2d29ea arm64: dts: imx8mm-venice-gw7903: Increase HS400 USDHC clock speed
3b94e93f86e6 arm64: dts: imx8mn-venice-gw7902: Increase HS400 USDHC clock speed
a81c22fbb48a arm64: dts: imx8mm-venice-gw7902: Increase HS400 USDHC clock speed
59d34e1fa7de arm64: dts: imx8mm-venice-gw7901: Increase HS400 USDHC clock speed
e1cf73b27bcb arm64: dts: imx8mp-venice-gw702x: Increase HS400 USDHC clock speed
0edd7bba0263 arm64: dts: imx8mm-venice-gw700x: Increase HS400 USDHC clock speed
9820a07342b0 arm64: dts: lx2160a-qds: add the two on-board RGMII PHYs
16382fa39594 arm64: dts: add imx95-libra-rdk-fpsc board
8a6f28dab39c arm64: dts: imx8q: add linux,cma node for imx8qm-mek and imx8qxp-mek
ba73343b8812 arm64: dts: imx8: add capture controller for i.MX8's img subsystem
ea6b32baf520 arm64: dts: imx95: add jpeg encode and decode nodes
2a4634dc728b arm64: dts: imx93-phyboard-nash: Add PEB-WLBT-07 overlay
c080e7b9ddda arm64: dts: imx93-phyboard-segin: Add PEB-WLBT-05 overlay
1f7892023ef4 arm64: dts: imx93-phyboard-segin: Add PEB-EVAL-01 overlay
faa5aade74a9 arm64: dts: imx93-phycore-som: Add RPMsg overlay
07780fa4aed1 arm64: dts: freescale: tqmls10xx: Add vdd-supply for spi-nor flash
8e3492338e8b arm64: dts: freescale: tqmls10xx-mbls10xxa: Add vdd-supply for i2c mux
271103d977c9 arm64: dts: tqmls1046a: Enable SFP interfaces
25f7bd3b4a47 arm64: dts: tqmls1043a: Enable SFP interface
54f5caa98df8 arm64: dts: tqmls10xxa: Move SFP cage definition to common place
e715bb94e263 arm64: dts: fsl-ls1088a: Remove superfluous address and size cells
c82c1751f804 arm64: dts: fsl-ls1046a: Remove superfluous address and size cells
ebcd19d6347a arm64: dts: fsl-ls1043a: Remove superfluous address and size cells
17c7cc47affb arm64: dts: imx94: add missing clock related properties to flexcan1
d60633ab78a3 arm64: dts: imx8mn: Configure DMA on UART2
7d4ebc6b315b arm64: dts: imx8mm: Configure DMA on UART2
6d1fccdc8f60 arm64: dts: fsl-ls1046a: Add missing DMA entries for I2C & LPUART
7495eeebbd34 arm64: dts: fsl-ls1043a: Add missing DMA entries for I2C & LPUART
e06f4e76e905 arm64: dts: freescale: imx93-phycore-som: Add watchdog ext-reset-output pin
d58bd9b4a79b arm64: dts: imx8mn-beacon: Fix HS400 USDHC clock speed
c694a7bc8cf3 arm64: dts: imx8mm-beacon: Fix HS400 USDHC clock speed
6743b8d488e1 arm64: dts: tqma8mpql-mba8mpxl-lvds: Rename overlay to include display name
a37af13d15c8 arm64: dts: imx8qm-mek: support revd board's wm8962 codec
7a3fbd740ca5 arm64: dts: imx8qxp-mek: support wcpu board's wm8962 codec
7e34086585b9 arm64: dts: imx8mp-evk: Use fsl-asoc-card to replace simple card
83f3bf720be9 arm64: dts: imx93: add edma error interrupt support
ebf5c781f77d arm64: dts: freescale: imx8mp-toradex-smarc: add fan cooling levels
181479b67e8a arm64: dts: imx8mp: Configure VPU clocks for overdrive
59f683a9ab68 arm64: dts: imx8mp-nominal: Explicitly configure nominal VPU clocks
8a232cb5a7fa arm64: dts: imx8mp: fix VPU_BUS clock setting
eb10431b8e66 arm64: dts: imx8mp: drop gpcv2 vpu power-domains and clocks
60e50a08da9b arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support
a248219a8875 ARM: dts: mediatek: add basic support for Lenovo A369i board
bfd569da9873 ARM: dts: mediatek: add basic support for JTY D101 board
2a4d4ef273b2 ARM: dts: mediatek: add basic support for MT6572 SoC
23404121bdd4 dt-bindings: arm: mediatek: add boards based on the MT6572 SoC
a4c8dd9520f6 dt-bindings: vendor-prefixes: add JTY
e0c23527ba98 dt-bindings: watchdog: mediatek,mtk-wdt: add MT6572
b2b61a2db095 dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572
804ab7c7d85d ARM: dts: imx6-gw: Replace license text comment with SPDX identifier
03bac12b32b2 ARM: dts: imx6ul-kontron-sl-common: Fix QSPI NAND node name
ad2593118243 ARM: dts: imx6ul-kontron-sl-common: Add SPI NOR partitions
4885f805e158 ARM: dts: imx6ul-kontron-bl-common: Fix RTS polarity for RS485 interface
d1b91e76690e dt-bindings: add imx95-libra-rdk-fpsc
a0409bf40ae5 arm64: dts: ti: k3-am69-sk: Add idle-states for remaining SERDES instances
673bf0fe91bc arm64: dts: ti: k3-am62a7-sk: add boot phase tags
0b61c356e6ad arm64: dts: ti: k3-am654-base-board: add boot phase tags
7d711c316bdb arm64: dts: ti: k3-am65: add boot phase tags
e177b1c9de01 dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2
1c5060689b34 dt-bindings: net: ftgmac100: Add resets property
5193dd5fa141 dt-bindings: net: sophgo,sg2044-dwmac: Add support for Sophgo SG2042 dwmac
5ce5f07b5508 dt-bindings: net: dsa: mediatek,mt7530: add internal mdio bus
583ebba08917 dt-bindings: net: dsa: mediatek,mt7530: add dsa-port definition for mt7988
0f557ac7ccfe dt-bindings: net: mediatek,net: add sram property
cffbaf9b81e2 dt-bindings: net: mediatek,net: allow irq names
a76ffe63b15c dt-bindings: net: mediatek,net: allow up to 8 IRQs
6bb228560999 dt-bindings: net: mediatek,net: update mac subnode pattern for mt7988
97de60cfbce0 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
b9da9213ade8 arm64: dts: st: remove empty line in stm32mp251.dtsi
64063fff5ffb arm64: dts: st: fix timer used for ticks
4c7a19b4cb33 regulator: Merge tps6594 driver changes
daad99af0822 dt-bindings: mfd: ti,tps6594: Add TI TPS652G1 PMIC
8386b729544f dt-bindings: media: cdns,csi2rx.yaml: Add optional interrupts for cdns-csi2rx
b29392c6d2f8 arm64: dts: rockchip: Enable HDMI receiver on RK3588 EVB1
d54023e2d503 arm64: dts: rockchip: fix PHY handling for ROCK 4D
a3f230874d3a arm64: dts: rockchip: Enable mipi dsi on rk3568-evb1-v10
cf9888548489 arm64: dts: rockchip: Add UFS support on the ROCK 4D
7903089bd476 arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot
24844a9efccd arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot
f4fdd87dbb41 arm64: dts: ti: k3-am62p5-sk: Add bootph-all property to enable Ethernet boot
3939a611e8bc arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot
a3f5e9fa0441 arm64: dts: ti: Add support for AM62D2-EVM
7a38d687cc98 arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCs
f2166a890cbb dt-bindings: arm: ti: Add AM62D2 SoC and Boards
aa589db3ac8e arm64: dts: ti: Add bootph property to nodes at source for am62a
24acc0cda0ca dt-bindings: ethernet-phy: add MII-Lite phy interface type
de5faa29496a dt-bindings: dpll: Add support for Microchip Azurite chip family
be3edb0ba9c7 dt-bindings: dpll: Add DPLL device and pin
6951965726e3 dt-bindings: net: Add support for Sophgo CV1800 dwmac
57ec540c0009 dt-bindings: memory: renesas,rzg3e-xspi: Document RZ/V2H(P) and RZ/V2N support
397d62e38e6d dt-bindings: arm: sunxi: Combine board variants into enums
94f9ccddf8d2 ARM: tegra: Add device-tree for ASUS VivoTab RT TF600T
966adacf22f9 dt-bindings: serial: rsci: Update maintainer entry
311412a89e25 dt-bindings: serial: renesas,rsci: Add optional secondary clock input
107315cef7f1 dt-bindings: serial: sh-sci: Document r8a78000 bindings
49773b5da84b dt-bindings: power: qcom,rpmpd: document the Milos RPMh Power Domains
89e711f0ab70 arm64: dts: ti: k3-am62p-verdin: Adjust temperature trip points
6d8d2fd35d79 arm64: dts: ti: k3-am62p-j722s: Enable freq throttling on thermal alert
96816c0c1cda Merge tag 'pm-runtime-6.17-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
4c2695cf19b3 arm64: dts: ti: k3-j784s4-j742s2-main-common: Add PBIST_14 node
8d9287a162e7 dt-bindings: soc: ti: bist: Add BIST for K3 devices
2708025daa67 arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR support
3112e1658091 arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file
6dfe3e70a454 arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1
b74625437e2b riscv: dts: spacemit: Move eMMC under storage-bus for K1
106a2d7182d9 riscv: dts: spacemit: Move UARTs under dma-bus for K1
37db9248d762 riscv: dts: spacemit: Add DMA translation buses for K1
d9accb54a587 riscv: dts: spacemit: add pwm14_1 pinctrl setting
0603708cb366 riscv: dts: spacemit: add PWM support for K1 SoC
23afee5fb806 arm64: dts: ti: k3-am62p-verdin: fix PWM_3_DSI GPIO direction
e05ddcb61514 arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by default
d8f96fe1e4b5 dt-bindings: net: altr,socfpga-stmmac.yaml: add minItems to iommus
e38f508615bd net: dt-bindings: ixp4xx-ethernet: Support fixed links
75d68220cfff dt-bindings: interrupt-controller: Add Arm GICv5
33b7328bd67b Merge tag 'drm-msm-next-2025-07-05' of https://gitlab.freedesktop.org/drm/msm into drm-next
10794b789986 docs: dt: writing-bindings: Consistently use single-whitespace
86a9bf4c4443 docs: dt: writing-bindings: Express better expectations of "specific"
0c8f9e02cd3b docs: dt: writing-bindings: Rephrase typical fallback (superset) usage
0f6503d69ae6 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
add55fc9ed19 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
7cd8bb1dc1cc arm64: dts: renesas: r9a09g057: Add XSPI node
531f2d9725b7 arm64: dts: renesas: r9a09g056: Add XSPI node
84f1df18dc5f Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-dts-for-v6.17
a4a0bc4dc3e9 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
8b67347d881d arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
66af74e1aa4d arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
c813a6ce829d arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
eb1e7e4e9e6e dt-bindings: rtc: nxp,lpc1788-rtc: add compatible string nxp,lpc1850-rtc
d9c9432709dc dt-bindings: rtc: move nxp,lpc3220-rtc to separated file from trivial-rtc.yaml
f7e641cf0882 dt-bindings: Move sophgo,cv1800b-rtc to rtc directory
c2ccc8724b7a arm: dts: ti: omap: Fixup pinheader typo
e6a0b772cb05 ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching
40e9787d1816 ASoC: soc-dapm: cleanups
01c983755f54 ARM: dts: marvell: kirkwood: use recent scl/sda gpio bindings
75df38d090a6 arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support
3a6357e27ba7 arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support
6a3deb51c9b5 arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
c7292550d3ab ARM: dts: imx6-karo: Replace license text comment with SPDX identifier
c134c3be2c58 arm64: dts: s32g: Add USB device tree information for s32g2/s32g3
8faccf139224 dt-bindings: usb: Add compatible strings for s32g2/s32g3
32caa97af9bf dt-bindings: gpio: pca95xx: add TI TCA6418
7158638bb3cd arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
a2a08c044349 arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
240182754e31 arm64: dts: mediatek: mt7988: add cci node
6e93e2385a19 dt-bindings: interconnect: add mt7988-cci compatible
74844cb5275e arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board
8289107f1c92 arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe
e4519cc918c5 arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks
f8de516be111 arm64: dts: mediatek: mt8186: Merge Voltorb device trees
034615aac7eb arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing
b0b73c2d7ae7 dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks
6b59c9ae290e dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries
ae2638c7d641 Merge tag 'pm-runtime-6.17-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm into gpio/for-next
bc9b5bf851b3 dt-bindings: pwm: Convert lpc32xx-pwm.txt to yaml format
56458f97f58d dt-bindings: pwm: argon40,fan-hat: Document Argon40 Fan HAT
5ec6557630fd dt-bindings: vendor-prefixes: Document Argon40
71c5a4bb4e89 dt-bindings: pwm: mediatek,mt2712-pwm: Add support for MT6991/MT8196
6240e06fc3e5 dt-bindings: pwm: convert lpc1850-sct-pwm.txt to yaml format
b535e7088d2f dt-bindings: pwm: adi,axi-pwmgen: Update documentation link
69d7e2a442d2 dt-bindings: pwm: sophgo: Add pwm controller for SG2044
af64f85f74b4 riscv: dts: sifive: unleashed/unmatched: Remove PWM controlled LED's active-low properties
e0be156f6035 dt-bindings: pwm: marvell,pxa-pwm: Add SpacemiT K1 PWM support
e49654c2f279 Merge tag 'pm-runtime-6.17-rc1'
b24aeebf87a0 arm64: dts: allwinner: t527: Add OrangePi 4A board
7f5a1f6e1eb9 arm64: dts: allwinner: a523: Add UART1 pins
952f9cbd7af1 arm64: dts: allwinner: a523: Move rgmii0 pins to correct location
ad8576fad7d4 arm64: dts: allwinner: a523: Move mmc nodes to correct position
15e4d9212ce3 dt-bindings: arm: sunxi: Add Xunlong OrangePi 4A board
12336bf96c72 dt-bindings: iio: adc: nxp,lpc3220-adc: allow clocks property
e65cbadc0548 dt-bindings: iio: adc: ad4851: add spi-3wire
4d9c51edc9b9 arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
e086fd8876f5 arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
9d9c6611c451 arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
208cce5857c4 ARM: dts: microchip: sama7g5: Add cache configuration for cpu node
509b99826913 ARM: dts: microchip: sama7d65: Add cache configuration for cpu node
f3d0e33299fd ARM: dts: microchip: sama5d4: Update the cache configuration for CPU
8941fbf6ba5b ARM: dts: microchip: sama5d3: Update the cache configuration for CPU
2eff3303da8d ARM: dts: microchip: sama5d2: Update the cache configuration for CPU
e7b18d4c2364 Merge merge point of tag 'usb-6.16-rc5' into usb-next
c38da1ad3c4f dt-bindings: opp: adreno: Update regex of OPP entry
677b04f5438a dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
e31a0e2df6d3 arm64: dts: amlogic: Enable the npu node for Alta and VIM3
607ef22a465f dts: arm64: amlogic: add S6 pinctrl node
9211f8207ece dts: arm64: amlogic: add S7D pinctrl node
ab5a66e09833 dts: arm64: amlogic: add S7 pinctrl node
15aac295b6bc arm64: dts: amlogic: Add Ugoos AM3
79c971501356 dt-bindings: arm: amlogic: Add Ugoos AM3
a6dec074934f arm64: dts: amlogic: Align wifi node name with bindings
a21c94e943cb dt-bindings: display/msm: qcom,sm8750-mdss: Add SM8750
109b054c5d62 dt-bindings: display/msm: qcom,sm8650-dpu: Add SM8750
d58d7037c611 dt-bindings: display/msm: dp-controller: Add SM8750
79c555201895 dt-bindings: display/msm: dsi-controller-main: Add SM8750
02e87e911953 dt-bindings: display/msm: dsi-phy-7nm: Add SM8750
792e2ba64bb0 ARM: dts: stm32: add stm32mp157f-dk2 board support
69778818ec62 dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
7643ccce963f ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
5b0e91604398 ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
bf70ebd8ffe1 dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
c76df445d8e2 ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
475d705400c1 ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
4bb10d43e4dc ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
b0cec331ce90 arm64: dts: st: add timer nodes on stm32mp257f-ev1
3784048145a5 arm64: dts: st: add timer pins for stm32mp257f-ev1
2030d965c281 arm64: dts: st: add timer nodes on stm32mp251
5e0382c920e9 ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
7f41efee603f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
1210620aaa38 arm64: dts: ti: k3-am62p-verdin: add SD_1 CD pull-up
49fb938f2aa0 ARM: dts: aspeed: yosemite4: add gpio name for uart mux sel
f80c1ece0727 ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMC
5739123deb47 dt-bindings: arm: aspeed: add Meta Santabarbara board
17e841eb8a01 ARM: dts: aspeed: bletchley: enable USB PD negotiation
6c20b3c5da78 ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodes
ac274dd83da4 ARM: dts: aspeed: harma: add mmc health
5f776e456b95 ARM: dts: aspeed: Harma: revise gpio bride pin for battery
285c16da7d59 ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoring
707670385616 ARM: dts: aspeed: harma: add fan board I/O expander
5cdab6370fb5 ARM: dts: aspeed: harma: add E1.S power monitor
4ac3caeab4d6 ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC management
4acc31107f44 Merge tag 'drm-misc-next-2025-07-03' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
3dfcfb15f3a4 riscv: dts: spacemit: add reset support for the K1 SoC
b1de41ddb12c Merge tag 'spacemit-reset-binding-for-6.17-1' of https://github.com/spacemit-com/linux
990c4c25e751 dt-bindings: pinctrl: stm32: Add missing blank lines
e6da1f46eb46 dt-bindings: pinctrl: convert nxp,lpc1850-scu.txt to yaml format
bfffde04584b arm64: dts: qcom: sm8150: Drop unrelated clocks from PCIe hosts
bccba5ad2d5e arm64: dts: qcom: sc8180x: Drop unrelated clocks from PCIe hosts
7d4d5736e895 dt-bindings: watchdog: fsl-imx-wdt: add compatible string fsl,ls1046a-wdt
3bd76858e231 Merge tag 'arm-soc/for-6.17/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
e5d755023dc6 ARM: dts: lpc32xx: Add #pwm-cells property to the two SoC PWMs
5c1cfc4da7e7 Merge tag 'arm-soc/for-6.17/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
376d0636861a dt-bindings: mtd: jedec,spi-nor: Add atmel,at26* compatible string
fe2b22926763 Merge tag 'renesas-dts-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
5aaa6a166e8d Merge tag 'renesas-dt-bindings-for-v6.17-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
7a374a9fc8f9 arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
9b8b632ab773 arm64: dts: lg: Add missing PL011 "uartclk"
1840478bd82c arm64: dts: lg: Refactor common LG1312 and LG1313 parts
da6dbfcc7301 dt-bindings: soc: spacemit: define spacemit,k1-ccu resets
bb90348d29a9 dt-bindings: mmc: Add sdhci compatible for qcs8300
0414ba944436 spi: dt-bindings: Convert marvell,orion-spi to DT schema
a56bc205230f dt-bindings: mmc: loongson,ls2k0500-mmc: Add compatible for Loongson-2K2000
3cc034e85df9 dt-bindings: mmc: Add Loongson-2K SD/SDIO/eMMC controller binding
dcdc40b6d229 mips: dts: qca: add wmac support
c66d6090a834 MIPS: mobileye: dts: eyeq5: add the emmc controller
cec254c8523d MIPS: mobileye: dts: eyeq6h: add the emmc controller
611c15d5e513 dt-bindings: mmc: renesas,sdhi: Document RZ/T2H and RZ/N2H support
c824773bddb3 dt-bindings: reset: Convert snps,dw-reset to DT schema
86485ac1b19d dt-bindings: media: qcom,x1e80100-camss: Fix isp unit address
728f8edb14ff dt-bindings: media: qcom,x1e80100-camss: Remove clock-lanes port property
7a573d543274 dt-bindings: media: qcom,x1e80100-camss: Add optional bus-type property
775c0a28cdd1 dt-bindings: media: qcom,x1e80100-camss: Tighten the property regex pattern
e73fc4fe22c1 Merge tag 'ib-mfd-gpio-input-pwm-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
2cdc59469372 dt-bindings: net: Convert socfpga-dwmac bindings to yaml
03396f2ec6d3 arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
b581622620e9 arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
8c9f5b0429a2 arm64: dts: renesas: Add Renesas R8A779H2 SoC support
2b6093a18f87 arm64: dts: renesas: Factor out Gray Hawk Single board support
c8fc0b439820 dt-bindings: soc: renesas: Document R-Car V4M-7 Gray Hawk Single
ec22ed6659ed Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
64c19295dba9 Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17
8fef4f6b3495 dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
0f1bcc2d243a dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
4380d39a0bfd ARM: dts: sun8i: v3: Add RGB666 LCD PD pins definition
d4241e745089 ARM: dts: sun8i: v3s: Add RGB666 LCD PE pins definition
6b354c7e0cba mips: dts: realtek: Add gpio block
c0d0aedd3de9 mips: dts: realtek: Add watchdog
dae2bc5616a8 mips: dts: realtek: Add switch interrupts
38394a11dfec mips: dts: cameo-rtl9302c: Add switch block
e4d0f8f0b485 MIPS: dts: ralink: gardena_smart_gateway_mt7688: Fix power LED
53804508fc88 MIPS: dts: ralink: mt7628a: Update watchdog node according to bindings
96b1d8882b30 MIPS: dts: ralink: mt7628a: Fix sysc's compatible property for MT7688
3a5d39e27fb7 dt-bindings: clock: mediatek,mtmips-sysc: Adapt compatible for MT7688 boards
e2714b69d705 ASoC: dt-bindings: qcom,sm8250: Add QCS8275 sound card
93001f7dcb85 ARM: dts: imx6ul: support Engicam MicroGEA GTW board
9ea985f294fc ARM: dts: imx6ul: support Engicam MicroGEA RMM board
b0e34d5a967c ARM: dts: imx6ul: support Engicam MicroGEA BMM board
acf9f66533f6 ARM: dts: imx6ul: support Engicam MicroGEA-MX6UL SoM
d23e9ea1eaac dt-bindings: arm: fsl: support Engicam MicroGEA GTW board
e50303295b76 dt-bindings: arm: fsl: support Engicam MicroGEA RMM board
aec517ade0f4 dt-bindings: arm: fsl: support Engicam MicroGEA BMM board
98ba73c32158 dt-bindings: net: convert nxp,lpc1850-dwmac.txt to yaml format
0f4043ab479c iio: adc: ad7173: add SPI offload support
d7b8723e5cc9 dt-bindings: trigger-source: add ADI Util Sigma-Delta SPI
84d8f9c362fd dt-bindings: mfd: adp5585: document reset gpio
362f91ed9a71 dt-bindings: mfd: adp5585: add properties for input events
a8629f7b1c76 dt-bindings: mfd: adp5585: document adp5589 I/O expander
56126147cf7f dt-bindings: mfd: adp5585: ease on the required properties
e89612b694cf dt-bindings: input: touchscreen: edt-ft5x06: Document FT8716 support
fcb3290cc9aa dt-bindings: input: touchscreen: convert tsc2007.txt to yaml format
2aa354161f52 dt-bindings: dsp: fsl,dsp: document 'access-controllers' property
6e293da49ad9 dt-bindings: bus: document the IMX AIPSTZ bridge
56370e58513a arm64: dts: imx93-11x11-evk: remove the duplicated pinctrl_lpi2c3 node
b2cf0ac6473f arm64: dts: imx93-11x11-evk: reduce the driving strength of net RXC/TXC
1f8f5eb35b99 arm64: dts: imx93-11x11-evk: disable all realtek ethernet phy CLKOUT
3f439f3e0847 arm64: dts: imx93-qsb/evk: add usdhc3 and lpuart5
c288a6c72f58 arm64: dts: imx93: remove eee-broken-1000t for eqos node
28a0f520481d arm64: dts: imx93-9x9-qsb: add IMU sensor support
bdbdeea06674 arm64: dts: freescale: imx8mp-var-som: Add EQoS support with MaxLinear PHY
fef47da29940 arm64: dts: imx8qm: add system controller watchdog support
43a9c5204a71 arm64: dts: imx95-19x19-evk: add GPIO reset for ethphy0
cfbae9c05739 arm64: dts: imx95-19x19-evk: adjust pinctrl settings for usdhc2
2d2d317cda64 arm64: dts: imx95-evk: add USB3 PHY tuning properties
e2984acda327 arm64: dts: imx95-19x19-evk: add adc0 flexcan[1,2] i2c[2,3] uart5 spi3 and tpm3
1b516b64f709 arm64: dts: freescale: imx93-var-som: update eqos support for MaxLinear PHY
236b3b5fa844 arm64: dts: imx8mp-venice-gw74xx: update name of M2SKT_WDIS2# gpio
ee2949900e0f arm64: dts: freescale: imx93-tqma9352: add memory node
a8cfb47ba83a arm64: dts: freescale: imx93-phyboard-nash: Move ADC vref to SoM
b4ab5602f093 dt-bindings: arm: fsl: add i.MX28 Amarula rmm board
58732bd8328b ARM: dts: mxs: support i.MX28 Amarula rmm board
54dad17c1416 ARM: dts: imx28: add pwm7 muxing options
7826f7be97d7 dt-bindings: serial: mediatek,uart: add MT6572
a6870cdf2262 dt-bindings: interrupt-controller: Convert fsl,mpic-msi to YAML
a39baf2874e1 riscv: dts: thead: Add PVT node
59dcbcb5dbe8 riscv: dts: thead: th1520: Add GPU clkgen reset to AON node
b7064204c34a arm: dts: omap: Add support for BeagleBone Green Eco board
97e7316298d4 dt-bindings: omap: Add Seeed BeagleBone Green Eco
1fc23c040c64 arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node
d6a683de0144 dt-bindings: display: panel: Make reset-gpio as optional for Raydium RM67200
c7b79f4c60ea dt-bindings: display: panel: Add Himax HX83112B
287b9ff3a30a dt-bindings: vendor-prefixes: document Shenzhen DJN Optronics Technology
5b00d9d7cef3 arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
f493d4244fb4 arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7
2c6901d159a6 arm64: dts: rockchip: enable PCIe on ROCK 4D
c3fcd8d33101 arm64: dts: rockchip: Enable HDMI receiver on CM3588
c0c64cb2bea6 arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
271c1ecee280 arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
b347f6353796 dt-bindings: display: vop2: Add optional PLL clock property for rk3576
0ec19b976d2f dt-bindings: media: imx258: inherit video-interface-devices properties
32656f2dd7f7 dt-bindings: media: ov8858: inherit video-interface-devices properties
0a479200fad0 media: dt-bindings: mt9m114: Add slew-rate DT-binding
afcd87416700 media: dt-bindings: sony,imx214: Deprecate property clock-frequency
8c02f74a820d media: dt-bindings: mipi-ccs: Refer to video-interface-devices.yaml
21dd16fda6ae arm64: dts: exynos: gs101: switch to gs101 specific reboot
692223514aae arm64: dts: exynos: gs101-pixel-common: add main PMIC node
92a8f685b654 arm64: dts: exynos: gs101: ufs: add dma-coherent property
221da32f58b1 Merge 6.16-rc4 into tty-next
c0f052a89615 arm64: dts: imx95: add SMMU support for NETC
b5ed179c47d0 arm64: dts: imx943-evk: Add PDM microphone sound card support
bd71324d2afc arm64: dts: imx943-evk: add bt-sco sound card support
e22973f9644c arm64: dts: imx943-evk: add sound-wm8962 support
ba65c43c3568 arm64: dts: imx943-evk: add i2c io expander support
2364aebb71bb arm64: dts: imx943-evk: add lpi2c support
0b36a8496df3 arm64: dts: imx94: Add micfil and mqs device nodes
47f22e04693c dt-bindings: serial: 8250: allow clock 'uartclk' and 'reg' for nxp,lpc1850-uart
bb6fa1f5823a dt-bindings: usb: genesys,gl850g: add downstream facing ports
fe67c5983537 dt-bindings: usb: genesys,gl850g: use usb-hub.yaml
9d866d360be9 dt-bindings: input: touchscreen: convert lpc32xx-tsc.txt to yaml format
d9e86831c9e7 ARM: dts: Fix up wrv54g device tree
c88d144e4ee0 dt-bindings: dsa: Rewrite Micrel KS8995 in schema
721733928299 dt-bindings: net: sun8i-emac: Add A100 EMAC compatible
26d787d538c0 dt-bindings: net/nfc: ti,trf7970a: Add ti,rx-gain-reduction-db option
c4e889a39fbe dt-bindings: net: convert lpc-eth.txt yaml format
9d619f67ea06 dt-bindings: reset: sophgo: Add CV1800B support
390a51a896e0 dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/V2N SoC support
1ab195547189 dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
74f427003123 dt-bindings: reset: add support for canaan,k230-rst
bdfa6cf09cc8 dt-bindings: leds: lp50xx: Document child reg, fix example
0481e0a9c242 arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
d358bcfbc85a arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
3b48424bb12d arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
1067406bccda dt-bindings: net: Document support for Airoha AN7583 MDIO Controller
5d19097df3ab dt-bindings: memory-controller: Define fallback compatible
3a12dc8d7019 dt-bindings: interrupt-controller: Add arm,armv7m-nvic and fix #interrupt-cells
977be08b2098 dt-bindings: trivial-devices: add compatible string nxp,isp1301 from isp1301.txt
faae60a9136d dt-bindings: net: Rename renesas,r9a09g057-gbeth.yaml
acc53bb0cab4 Merge tag 'drm-misc-next-2025-06-26' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
253782c324ed dt-bindings: phy: qcom,snps-eusb2-repeater: Remove default tuning values
0ba1a407aad6 dt-bindings: phy: apm,xgene-phy: Remove trailing whitespace
29f6bd159cad spi: dt-bindings: add nxp,lpc3220-spi.yaml
563a067ae378 dt-bindings: net: wireless: ath11k-pci: describe firmware-name property
3dafddbf2214 dt-bindings: net: wireless: ath9k: add WIFI bindings
5a46d78c27c7 arm64: dts: qcom: x1-asus-zenbook: support sound
4820d1a59ead arm64: dts: qcom: x1-asus-zenbook: fixup GPU nodes
17d54e8cff64 dt-bindings: iio: adc: ad7768-1: add trigger-sources property
f1a36c705c57 dt-bindings: iio: adc: ad7768-1: Document GPIO controller
6d62b06711b2 dt-bindings: iio: adc: ad7768-1: document regulator provider property
f94145ede4c6 dt-bindings: trigger-source: add generic GPIO trigger source
b5103f279f65 dt-bindings: iio: adc: add ad7405
72d91eb75105 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
4a0d83820fdf arm64: dts: renesas: r9a09g047: Add GBETH nodes
3485db855114 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Rename fixed regulator node names
66a9960e5871 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add RAA215300 PMIC
062f9e2c026a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Add RAA215300 PMIC
3cfe736f1e40 dt-bindings: interrupt-controller: Add MIPS P8700 aclint-sswi
3cd935575bee dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example
669d2c02c393 dt-bindings: display: ti: Add schema for AM625 OLDI Transmitter
7b4c77851db5 dt-bindings: display: ti,am65x-dss: Re-indent the example
7fe4a35ce8ca arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 node
c6a9ae83e762 arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-C
a0ad301286a9 arm64: dts: qcom: sm6115: add debug UART pins
2c030b5460a9 dt-bindings: trivial-devices: Add Analog Devices ADT7411
34cb86fcdff2 Add few updates to the STM32 SPI driver
d16f0509fbae ARM: dts: microchip: sam9x7: Add LVDS controller
dc59315540b6 ASoC: Standardize ASoC menu
717b4dc30bb3 arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
0d47606fb8d9 ARM: dts: s5pv210: Align i2c-gpio node names with dtschema
ae5dcb68953b ARM: dts: exynos: Align i2c-gpio node names with dtschema
fc41e79c8d7c dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset
97166fd1f53d dt-bindings: firmware: thead,th1520: Add resets for GPU clkgen
9c5a0a7d84d4 dt-bindings: net: cdns,macb: add sama7d65 ethernet interface
989c7d86c01f spi: dt-bindings: stm32: deprecate `st,spi-midi-ns` property
65f0c52f9155 spi: dt-bindings: stm32: update bindings with SPI Rx DMA-MDMA chaining
3b18f58612bb dt-bindings: usb: dwc2: rename sophgo usb compatible string
37b9182375b9 dt-bindings: gnss: u-blox: add u-blox,neo-9m compatible
aeb89b24ad7e dt-bindings: mmc: cdns: add Mobileye EyeQ MMC/SDHCI controller
eb7dca9a7276 dt-bindings: mmc: mxs-mmc: change ref to mmc-controller-common.yaml from mmc-controller.yaml
d3ef944175aa dt-bindings: pse: tps23881: Clarify channels property description
54965f2a3351 dt-bindings: soc: renesas: Document RZ/T2H Evaluation Board part number
4e1c8311bf0d ARM: dts: microchip: sama5d2_icp: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
f6e4727e66e0 ARM: dts: microchip: sama5d27_wlsom1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
1025e2432dc1 ARM: dts: microchip: sama5d27_som1: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
346177955338 ARM: dts: microchip: sam9x60ek: rename spi-cs-setup-ns property to spi-cs-setup-delay-ns
040ecf520251 dt-bindings: net: convert qca,qca7000.txt yaml format
da41efa1472c Revert "ARM: dts: Update pcie ranges for dra7"
86e3aa4733ed ARM: dts: omap: am335x: Use non-deprecated rts-gpios
dcc259a92bf1 spi: microchip-core-qspi: Add regular transfers
689d9094a731 dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support
795bfa427a40 regulator: dvfsrc: Add support for MT8196 and
0c92dc5fb726 dt-bindings: regulator: mediatek-dvfsrc: Add MT8196 support
40062b24de96 dt-bindings: regulator: mediatek-dvfsrc: Add MT6893 support
3ea17e80490b dt-bindings: PCI: brcm,stb-pcie: Add num-lanes property
1a3a8073faf0 dt-bindings: PCI: qcom,pcie-sm8150: Drop unrelated clocks from PCIe hosts
ead3a65c4352 dt-bindings: PCI: qcom,pcie-sc8180x: Drop unrelated clocks from PCIe hosts
23ba48ce4f3d dt-bindings: crypto: Convert ti,omap4-des to DT schema
f3dc660ef7dd dt-bindings: crypto: Convert ti,omap2-aes to DT schema
b339218b8279 dt-bindings: rng: atmel,at91-trng: add sama7d65 TRNG
ff643bb28541 dt-bindings: crypto: add sama7d65 in Atmel TDES
0f0c72dc98dc dt-bindings: crypto: add sama7d65 in Atmel SHA
8462bd595120 dt-bindings: crypto: add sama7d65 in Atmel AES
76b9ac22e92f dt-bindings: crypto: fsl,sec-v4.0: Add power domains for iMX8QM and iMX8QXP
8639cd6d493b powerpc/microwatt: Correct ISA version number in device tree
5a69b5d0f9d4 ARM: dts: at91-sama5d27_wlsom1: Improve the Wifi compatible
b38f516e544a ARM: dts: microchip: gardena-smart-gateway: Fix power LED
a7efef227924 ARM: dts: microchip: sam9x7: Add clock name property
0c5aec276273 ARM: dts: microchip: sama7d65: Add clock name property
6fe4b2852827 ARM: dts: microchip: sama7g5: Adjust clock xtal phandle
3f1852d5065d ARM: dts: microchip: sam9x7: Add HLCD controller
5e5f78f26a1c ARM: dts: microchip: sama7d65: Enable CAN bus
9f891644a466 ARM: dts: microchip: sama7d65: Clean up extra space
e458631c8156 ARM: dts: microchip: sama7d65: Add CAN bus support
a2d173f4f06a ARM: dts: microchip: sama7d65: Add PWM support
e8cb36704dcf ARM: dts: microchip: sama7d65: Add crypto support
fad2776b7baf ARM: dts: microchip: use recent scl/sda gpio bindings
cfa530559e94 dt-bindings: power: supply: Drop redundant monitored-battery ref
4a278ae395fb dt-bindings: power: supply: summit,smb347: Add missing power-supply ref
1b193da31601 dt-bindings: power: supply: richtek,rt5033: Add missing power-supply ref
5b64ac18febc dt-bindings: power: supply: qcom,pmi8998: Add missing power-supply ref
f09e89e71f18 dt-bindings: power: supply: bq256xx: Add missing power-supply ref
561c50eeff1b dt-bindings: power: supply: bq2515x: Add missing power-supply ref
1c2a6f716763 arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC
6e8c6721786a dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC
d788cdf18afe arm64: dts: rockchip: Enable GPU on Radxa E20C
16d867f13e38 arm64: dts: rockchip: Add GPU node for RK3528
c3a10091d51d arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"
a2ef24e102ed arm64: dts: ti: k3-j722s-main: Add audio-refclk0 node
1d53c6646d99 arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single size
307b8ee66245 arm64: dts: ti: k3-am62a7-sk: Describe the SPI NAND
e0da88bbe5dc arm64: dts: ti: k3-j721s2-main: Add McASP nodes
f72c8b39a660 arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMI
4228071de8ea arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C buses
9f3a0581be0a arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet ports
0067f17cbb71 arm64: dts: mediatek: mt8370: Enable gpu support
fd8a8a611df3 dt-bindings: gpu: mali-bifrost: Add compatible for MT8370 SoC
8a87dd54887f media: dt-bindings: nxp,imx8-jpeg: Add compatible strings for IMX95 JPEG
a811534390f1 dt-bindings: media: convert fsl-vdoa.txt to yaml format
7c1831c97562 arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck
e65d94e8c6e4 arm64: dts: rockchip: add label to first port of ISP on px30
49bd59bda613 arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP
8f0855aaa6a1 dt-bindings: dma: qcom,gpi: Document the sc8280xp GPI DMA engine
de8e8cacccbf arm64: dts: s32g: add RTC node
2eff8e3eb821 arm64: dts: Add DSPI entries for S32G platforms
527d37438b73 arm64: dts: freescale: imx93-phyboard-segin: Set ethernet1 alias
e9c4ed1380e5 arm64: dts: freescale: imx93-phycore-som: Move ethernet0 alias to SoM
19fc892ae830 arm64: dts: tqma8mpql: Add EASRC support
10d58add28d4 arm64: dts: tqma8mnql: Add EASRC support
9684884f9cc2 arm64: dts: freescale: Add the BOE av123z7m-n17 variant of the Moduline Display
36d39a81979d arm64: dts: freescale: Add the BOE av101hdt-a10 variant of the Moduline Display
0ab9cec49c0a arm64: dts: freescale: Add the GOcontroll Moduline Display baseboard
96478662ba59 arm64: dts: freescale: add Ka-Ro Electronics tx8p-ml81 COM
a54ff893e9e6 arm64: dts: imx8mp: Add pinctrl config definitions
b0356e47aa51 arm64: dts: rockchip: Add power controller for RK3528
fa630610e626 arm64: dts: rockchip: enable USB on Sige5
32d30cc2bfc3 arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2
c7f61653a73d arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5
d5edb6dfb78c arm64: dts: rockchip: add SDIO controller on RK3576
a22bac5ead32 arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10
4e9c9ee05c23 dt-bindings: clock: convert lpc1850-ccu.txt to yaml format
5dab6d0666f8 arm64: dts: rockchip: Update the PinePhone Pro panel description
eaa75b56dcfb Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
64842d8e059f Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17
07f1f3844c5d Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17
e0ebadb2045d dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
949d0cfc7c44 dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
51071ab402e3 dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
3ec018584fa1 arm64: dts: renesas: rcar-gen3: Add bootph-all to sysinfo EEPROMs
fc5f0def788b arm64: dts: renesas: sparrow-hawk: Describe split PCIe clock
3a8905aac211 arm64: dts: renesas: r8a779g0: Describe PCIe root ports
6887bc8543b4 arm64: dts: renesas: ebisu: Add CAN0 support
fd8b44404cb0 ARM: dts: renesas: r9a06g032: Add second clock input to RTC
2371c2df77ea arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB2.0 support
b1400fa1ae46 arm64: dts: renesas: r9a09g056: Add USB2.0 support
1e6055b1bfba arm64: dts: renesas: r8a779g3-sparrow-hawk: Sort DTS
e46668c89ed4 ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe debug LEDs
b65d84ca5033 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB2.0 support
5105a55fda27 dt-bindings: serial: renesas,rsci: Document RZ/N2H support
717942ab9fdf dt-bindings: usb: renesas,usbhs: Add RZ/V2N SoC support
51e5237dc82f ARM: dts: vf: vf610-zii-cfu1: rename node name *-gpio to *-gpios
39b627463c2b ARM: dts: vf: vf-colibri-eval-v3: add power-supply for edt,et057090dhu
fd302676921b ARM: dts: vf: rename io-expander@20 to pinctrl@20
9bea7c6d261c ARM: dts: vf: remove redundant layer under iomux
e139807952b1 ARM: dts: vf: remove redundant pinctrl-names
d2e638640e96 ARM: dts: vf: remove reg property for arm pmu
8f8e41560419 ARM: dts: vfxxx: Correctly use two tuples for timer address
f98b63e7e4d4 dt-bindings: arm: fsl: Add GOcontroll Moduline Display
2c61daf98d93 arm64: dts: add ngpios for vf610 compatible gpio controllers
063fd6175ada ARM: dts: add ngpios for vf610 compatible gpio controllers
19c622072a55 dt-bindings: net: pse-pd: ti,tps23881: Add interrupt description
a956323691dc dt-bindings: net: pse-pd: microchip,pd692x0: Add manager regulator supply
49faac7c9fd8 dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema
2d92d14e9eef dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema
d2ce3c47d404 dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema
e37e069f8b0f dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema
9cf6d0ba0fdf dt-bindings: clock: Convert marvell,berlin2-clk to DT schema
bb06131b2ecc dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema
1fd176774ea2 dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema
a06036f72ced dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema
45f94b0de650 dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema
5a9f538c0e6b dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema
5a62a028d23b dt-bindings: clock: Convert lsi,axm5516-clks to DT schema
bb7d222956f9 dt-bindings: clock: Convert img,pistachio-clk to DT schema
763873a48189 dt-bindings: clock: Convert brcm,bcm2835-cprman to DT schema
cee9659816b4 dt-bindings: clock: Convert cirrus,ep7209-clk to DT schema
f10c6670b7e2 dt-bindings: clock: Convert APM XGene clocks to DT schema
bff50be25ecd dt-bindings: clock: Convert axis,artpec6-clkctrl to DT schema
7debe9917c80 dt-bindings: clock: Convert brcm,bcm53573-ilp to DT schema
37248ce61324 Merge branch '20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com' into clk-for-6.17
945db09189dc dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
71f2de4a034f arm64: dts: qcom: sm8650: add iris DT node
d496cf29098a arm64: dts: qcom: msm8976-longcheer-l9360: Add initial device tree
ab1f53f63414 arm64: dts: qcom: msm8976: Add sdc2 GPIOs
b003f5c6b91d dt-bindings: arm: qcom: Add MSM8976 BQ Aquaris X5 Plus
a260177d0411 arm64: dts: qcom: msm8976: Make blsp_dma controlled-remotely
6de07b6f15ca ASoC: dt-bindings: cirrus,cs42xx8: add 'port' property
fb3447bb3b35 arm64: dts: qcom: sa8775p: Correct the interrupt for remoteproc
3058275a342c dt-bindings: rockchip: pmu: Add compatible for RK3528
50db66235f2b dt-bindings: power: rockchip: Add support for RK3528
33ceeabccc61 dt-bindings: pinctrl: eswin: Document for EIC7700 SoC
64e88c0fed96 arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
b10142d10119 dt-bindings: gpio: arm,pl061: Drop interrupt properties as required
469d40ff1fc6 arm64: dts: exynosautov920: Add DT node for all SPI ports
d6e199e49db3 dt-bindings: pinctrl: stm32: Add RSVD mux function
fcd55a37ae62 dt-bindings: mtd: convert nxp-spifi.txt to yaml format
b88ae50b4a3f media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings
5ea6161f602d media: dt-bindings: Add binding doc for i.MX8QXP and i.MX8QM ISI
12f918ab5174 arm64: dts: qcom: sm8550: Add support for camss
3b8507884db9 arm64: dts: qcom: qcs615: disable the CTI device of the camera block
f605900d6de0 arm64: dts: qcom: qcs615-ride: enable remoteprocs
8093aa08d5a7 arm64: dts: qcom: qcs615: add ADSP and CDSP nodes
cff0cbfd4ffc arm64: dts: qcom: qcs615: Add IMEM and PIL info region
1454cb2395b1 arm64: dts: qcom: qcs615: Add mproc node for SEMP2P
d41393450043 arm64: dts: qcom: Add support for X1-based Asus Zenbook A14
455400158e35 arm64: dts: qcom: sc7180: Expand IMEM region
b73a5a409b33 arm64: dts: qcom: sdm845: Expand IMEM region
ed819d4948e0 dt-bindings: sram: qcom,imem: Add a number of missing compatibles
46d41941b590 arm64: dts: qcom: qcs615: fix a crash issue caused by infinite loop for Coresight
bcd405d4605c arm64: dts: qcom: sm6350: add APR and some audio-related services
cf84790a7bc1 arm64: dts: qcom: qcm2290: Add CAMSS node
71de0b13f5f4 arm64: dts: qcom: sa8775p-ride: enable video
f3c905ddb143 arm64: dts: qcom: sa8775p: add support for video node
2ea4d1a862e7 arm64: dts: qcom: sa8775p: Add CPU OPP tables to scale DDR/L3
f57f90da02fd arm64: dts: qcom: sa8775p: add EPSS l3 interconnect provider
484acd85064e arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 QRD board
08d016ce62b5 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 MTP
21f3bb719d06 arm64: dts: qcom: sm8750: Add UFS nodes for SM8750 SoC
a4f170b96c2b arm64: dts: qcom: apq8016-sbc-d3-camera: Convert to DT overlay
96ffdf9514de arm64: dts: qcom: x1e80100-dell-xps-9345: Add WiFi/BT pwrseq
81e24b484d8f Merge tag 'drm-misc-next-2025-06-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
7c6c4e986b5e dt-bindings: arm: cpus: Add Kryo 470 CPUs
c3e977592183 dt-bindings: sram: qcom,imem: Add the SM7150 compatible
ff4ba6b971ae dt-bindings: soc: qcom: aoss-qmp: Add the SM7150 compatible
3b86b00b2868 dt-bindings: soc: qcom,dcc: Add the SM7150 compatible
47cee050ea05 dt-bindings: soc: qcom: add qcom,qcs615-imem compatible
73bee717137b dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
6ad7e7635ff2 dt-bindings: PCI: qcom,pcie-sa8775p: Document QCS8300
fe9760407d9e dt-bindings: PCI: qcom,pcie-sm8150: Document QCS615
279926cf824c arm64: dts: qcom: Add QMP handle for qcom_stats
33b6b81327b2 arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: remove camcc status property
4dcdeb9e373b arm64: dts: qcom: sm8250: enable camcc clock controller by default
986337f7125b dt-bindings: remoteproc: qcom,sa8775p-pas: Correct the interrupt number
87d25536e261 dt-bindings: gpio: gpio-xilinx: Mark clocks as required property
7d9619784d4c dt-bindings: dmaengine: Add dma multiplexer for CV18XX/SG200X series SoC
949eaeb96a7b dt-bindings: clock: Add RaspberryPi RP1 clock bindings
d37ab6d3737b media: dt-bindings: media: renesas,vsp1: Document RZ/V2N SoC
c999498941a3 media: dt-bindings: media: renesas,fcp: Document RZ/V2N SoC
17e3b9892493 dt-bindings: phy: Add the M31 based eUSB2 PHY bindings
bc371e92d06e dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8750 to QMP PHY
335d8d9ff6e9 dt-bindings: phy: renesas,usb2-phy: Document RZ/V2N SoC support
b6272058c2ee dt-bindings: phy: Convert Marvell MVEBU PHYs to DT schema
3e6965af3886 dt-bindings: phy: Convert marvell,armada-380-comphy to DT schema
87f3979709df dt-bindings: phy: Convert ti,keystone-usbphy to DT schema
09d69b51d927 dt-bindings: phy: Convert ti,dm816x-usb-phy to DT schema
844acf2c998f dt-bindings: phy: Convert st,spear1310-miphy to DT schema
4bce5936846a dt-bindings: phy: Convert qca,ar7100-usb-phy to DT schema
ac5ef382d934 dt-bindings: phy: Convert motorola,mapphone-mdm6600 to DT schema
85e480d5fc84 dt-bindings: phy: Convert motorola,cpcap-usb-phy to DT schema
fe17837b8d9b dt-bindings: phy: Convert marvell,mmp2-usb-phy to DT schema
b126307f27dc dt-bindings: phy: Convert marvell,comphy-cp110 to DT schema
9bcbff3bd9d7 dt-bindings: phy: Convert marvell,berlin2-usb-phy to DT schema
0c82a7e3b08d dt-bindings: phy: Convert marvell,berlin2-sata-phy to DT schema
dc17572110df dt-bindings: phy: Convert lantiq,ase-usb2-phy to DT schema
b10685a3371a dt-bindings: phy: Convert img,pistachio-usb-phy to DT schema
408705e5a1ad dt-bindings: phy: Convert hisilicon,inno-usb2-phy to DT schema
727e67e12857 dt-bindings: phy: Convert hisilicon,hi6220-usb-phy to DT schema
1723ae98c198 dt-bindings: phy: Convert hisilicon,hix5hd2-sata-phy to DT schema
1dc8e1978b35 dt-bindings: phy: Convert brcm,sr-pcie-phy to DT schema
7cff50883378 dt-bindings: phy: Convert brcm,ns2-drd-phy to DT schema
93a177a9b1e9 dt-bindings: phy: Convert apm,xgene-phy to DT schema
55252481b031 dt-bindings: phy: samsung,mipi-video-phy: document exynos7870 MIPI phy
2b521ba242d3 dt-bindings: phy: samsung,usb3-drd-phy: Add exynos990 compatible
249194d3dfb7 dt-bindings: pci: Add Sophgo SG2044 PCIe host
88df97c059e6 arm64: dts: freescale: imx93-tqma9352: Remove unneeded GPIO hog
a73858b8f497 arm64: dts: freescale: imx93-tqma9352: Limit BUCK2 to 600mV
74609a3fb4f4 dt-bindings: net: renesas-gbeth: Add support for RZ/G3E (R9A09G047) SoC
ecbe9ffa03ea ARM: dts: imx7s-warp: Improve the Wifi description
b3cead4032a5 ARM: dts: imx7s-warp: Improve the Bluetooth description
d826170f23a8 arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
892f6f8d54b1 dt-bindings: clock: exynosautov920: add hsi2 clock definitions
fc73efed87ea dt-bindings: clock: exynosautov920: sort clock definitions
a698889e0340 ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
cc0cd2f62fba ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller
ba6b8fbd8f10 ARM: dts: vt8500: Use generic node name for the SD/MMC controller
4c2bee5a57aa ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size
618840988c7d ARM: dts: vt8500: Add node address and reg in CPU nodes
638f4396159a arm64: dts: exynos: add initial support for Samsung Galaxy S22+
cda58ddae028 arm64: dts: exynos: add initial support for exynos2200 SoC
ba78ccfb85f1 dt-bindings: arm: samsung: document g0s board binding
928cf7b4db3d ASoC: dt-bindings: mt8192-afe-pcm: Allow specifying reserved memory region
7f82922e67a2 ASoC: dt-bindings: mt8186-afe-pcm: Allow specifying reserved memory region
7b4cfbf9cb43 ASoC: dt-bindings: mt8173-afe-pcm: Allow specifying reserved memory region
76cd57f4055e ASoC: dt-bindings: mt8173-afe-pcm: Add power domain
e8ba4d8d36e5 ASoC: dt-bindings: Convert MT8173 AFE binding to dt-schema
f9ab470b7216 ARM: dts: qcom: msm8974-sony-xperia-rhine: Add alias for mmc0 & mmc1
9a441a5e784a ARM: dts: qcom: msm8974-hammerhead: Add alias for mmc0
ab2a3af6930a ARM: dts: qcom: msm8974-oneplus-bacon: Add alias for mmc0
13bab98ae230 ARM: dts: qcom: Add initial support for Sony Xperia Z Ultra (togari)
830c3bb76487 dt-bindings: arm: qcom: Add Sony Xperia Z Ultra (togari)
65ca47d47e86 ARM: dts: qcom: msm8974-sony-xperia-rhine: Move camera buttons to amami & honami
658cf0eaccff ARM: dts: qcom: msm8974-sony-xperia-rhine: Enable USB charging
23712e8754a3 arm64: dts: qcom: x1p42100: Fix thermal sensor configuration
aa97b937223a arm64: dts: qcom: sm8650: remove unused reg
822ac62b57ee arm64: dts: qcom: sm8750-qrd: Add sound (speakers, headset codec, dmics)
6a7ae2443826 arm64: dts: qcom: sm8750-mtp: Add sound (speakers, headset codec, dmics)
6f4d1bf469a1 arm64: dts: qcom: sm8750: Add Soundwire nodes
dd1d6dea4bb1 arm64: dts: qcom: x1e80100-hp-x14: amend order of nodes
9eeffdf93012 arm64: dts: qcom: x1e80100-hp-x14: remove unused i2c buses
87e775221157 arm64: dts: qcom: x1e80100-hp-x14: add usb-1-ss1-sbu-mux
22c3ee0b6723 dt-bindings: clock: Convert brcm,bcm63xx-clocks to DT schema
5959214b449a dt-bindings: clock: ti: add ti,autoidle.yaml reference
be74285c8495 dt-bindings: clock: ti: Convert fixed-factor-clock to yaml
795aeb632bcf dt-bindings: clock: ti: Convert autoidle binding to yaml
81cf11f33bdc ARM: dts: qcom: msm8960: use macros for interrupts
b8acdc312e48 spi: dt-bindings: mediatek,spi-mt65xx: Add support for MT6991/MT8196 SPI
b27e030826ed arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card
f1bdce636304 arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend
4c6cbd4937e7 arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend
0bbc5f383e6f arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend
459a4687b473 arm64: dts: mediatek: mt8173: Reserve memory for audio frontend
bcfa2c4f812f arm64: dts: imx8mp: Enable gpu passive throttling
4bee3e87ff2b arm64: dts: imx95: correct i3c node in imx95
f4253a424db7 Merge drm/drm-next into drm-misc-next
67be89b70d90 ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
b38511e07580 dt-bindings: arm: aspeed: add Nvidia's GB200NVL BMC
c9ef33bddfd0 ARM: dts: aspeed: catalina: Enable MCTP support for NIC management
5bea70972e95 ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and address
5340d8724879 ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses
917b91ebae04 ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodes
0872eae37927 ARM: dts: aspeed: catalina: Add second source HSC node support
30621d6376f4 ARM: dts: aspeed: catalina: Add second source fan controller support
23a5060692bc ARM: dts: aspeed: catalina: Add fan controller support
c9680d1b9907 ARM: dts: aspeed: catalina: Add MP5990 power sensor node
43d4786d6d8d ARM: dts: aspeed: catalina: Add Front IO board remote thermal sensor
084d47454493 ARM: dts: aspeed: catalina: Add IO Mezz board thermal sensor nodes
5038976dd89a ARM: dts: aspeed: system1: Disable gpio pull down
a50225982fba ARM: dts: aspeed: system1: Mark GPIO line high/low
50fd31ea857a ARM: dts: aspeed: system1: Remove VRs max8952
907d0214bef2 ARM: dts: aspeed: system1: Update LED gpio name
7a218d1c5197 ARM: dts: aspeed: system1: Reduce sgpio speed
9d816c14e2c1 ARM: dts: aspeed: system1: Add GPIO line name
b78c314eda75 ARM: dts: aspeed: system1: Add IPMB device
4dbb7162e72d dt-bindings: ipmi: Add binding for IPMB device
58cf50957126 ARM: dts: aspeed: bletchley: remove unused ethernet-phy node
e2d77b735d13 ARM: dts: aspeed: Align GPIO hog name with bindings
7827afbe3914 ARM: dts: aspeed: Remove swift machine
a888a5efe1c2 dt-bindings: remoteproc: qcom,sm8150-pas: Document QCS615 remoteproc
69d13fabcaaf arm64: dts: qcom: Add camera clock controller for sc8180x
a9d6cb6c0fbe Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into arm64-for-6.17
531ad909582b Merge branch '20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com' into clk-for-6.17
db7047b5c166 dt-bindings: clock: Add Qualcomm SC8180X Camera clock controller
85694e07d677 dt-bindings: clock: qcom: Add missing bindings on gcc-sc8180x
0b4116099b60 arm64: dts: qcom: sm6350: Add video clock controller
c685c753be9d arm64: dts: qcom: qcs8300-ride: enable video
b80f475be983 arm64: dts: qcom: qcs8300: add video node
e08e7b76aa1e dt-bindings: clock: qcom,sm8450-camcc: Move sc8280xp camcc to sa8775p camcc
4d05467482c8 dt-bindings: clock: qcom,sm8450-camcc: Allow to specify two power domains
895f435e10e9 dt-bindings: clock: qcom,sm8450-videocc: Add MXC power domain
bc791dcd8483 arm64: dts: qcom: sa8775p-ride: add anx7625 DSI to DP bridge nodes
4098c5a2bf59 arm64: dts: qcom: sa8775p: add Display Serial Interface device nodes
0e31d061c9c0 arm64: dts: broadcom: northstar2: Drop GIC V2M "interrupt-parent"
ea1885c9fd30 arm64: dts: qcom: x1e80100: Add missing 'global' PCIe interrupt
14ad59d4559f arm64: dts: qcom: sar2130p: Add 'global' PCIe interrupt
0a47f45ad43a arm64: dts: qcom: sc8180x: Add 'global' PCIe interrupt
94ff2d21c06d arm64: dts: qcom: ipq6018: Add missing MSI and 'global' IRQs
420964cc89e0 arm64: dts: qcom: ipq8074: Add missing MSI and 'global' IRQs
6d1521f0fc17 arm64: dts: qcom: msm8998: Add missing MSI and 'global' IRQs
9da0fdcbce25 arm64: dts: qcom: msm8996: Add missing MSI SPI interrupts
275a1383fcdf arm64: dts: qcom: sdm845: Add missing MSI and 'global' IRQs
22e63cea7b60 arm64: dts: qcom: sc7280: Add 'global' PCIe interrupt
28bef8454e3d arm64: dts: qcom: sa8775p: Add 'global' PCIe interrupt
c18c33f1c365 arm64: dts: qcom: sm8350: Add 'global' PCIe interrupt
30dd461fe360 arm64: dts: qcom: sm8250: Add 'global' PCIe interrupt
5c8dac48ba74 arm64: dts: qcom: sm8150: Add 'global' PCIe interrupt
bb38e4d566a8 ARM: dts: qcom: Align wifi node name with bindings
0b05f902b191 dt-bindings: pinctrl: rockchip: increase max amount of device functions
e09ea8c6b2f4 dt-bindings: ili9881c: Document 7" Raspberry Pi 720x1280
d8786b38477d dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for S7/S7D/S6
ac3bc668fd07 dt-bindings: display: st7701: Add Winstar wf40eswaa6mnn0 panel
998a197154ea dt-bindings: display: visionox-rm69299: document new compatible string
8f0d68ed872a arm64: dts: rockchip: convert rk3562 to their dt-binding constants
509e0c2fabe8 arm64: dts: rockchip: Add Luckfox Omni3576 Board support
28cf288916a0 dt-bindings: arm: rockchip: Add Luckfox Omni3576 and Core3576 bindings
9c61e9d15269 dt-bindings: vendor-prefixes: Add luckfox prefix
2ab598cbc1ba arm64: dts: rockchip: Remove workaround that prevented Turing RK1 GPU power regulator control
68888e37d9fb arm64: dts: rockchip: add overlay for RockPro64 screen
f1ab980e061c Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = <1> for RZ/G3S"
d5b5838ba286 dt-bindings: clock: rzg2l: Drop power domain IDs
eb2482bd3a71 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17
c80e0b36f0b1 dt-bindings: memory-controllers: convert arm,pl172.txt to yaml format
6cf75590b12d dt-bindings: soc: samsung: exynos-pmu: Constrain google,pmu-intr-gen-syscon
9505fc5dd862 dt-bindings: gpio: convert nxp,lpc1850-gpio.txt to yaml format
54fb0929cc99 dt-bindings: gpio: convert gpio-74xx-mmio.txt to yaml format
a3e905523cd5 dt-bindings: gpio: convert gpio-pisosr.txt to yaml format
1040128bb18a arm64: dts: renesas: r9a09g057: Add USB2.0 support
a2a9c525081e arm64: dts: renesas: r9a09g047e57-smarc: Enable CRU, CSI support
21b5186a7f3e arm64: dts: renesas: renesas-smarc2: Enable I2C0 node
313bfdd58194 arm64: dts: renesas: r9a09g047e57-smarc: Add I2C0 pincontrol
c4a0b4786c56 arm64: dts: renesas: r9a09g047: Add CRU, CSI2 nodes
942d44d91446 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable Mali-G31 GPU
df4a18da3850 arm64: dts: renesas: r9a09g056: Add Mali-G31 GPU node
97126d793150 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable WDT1
aa49b82d292a arm64: dts: renesas: r9a09g056: Add WDT0-WDT3 nodes
0fd2a920a15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable RIIC controllers
a9e1b1c51a2e arm64: dts: renesas: r9a09g056: Add RIIC controllers
8620f503d15b arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable OSTM timers on RZ/V2N EVK
7edd14aa50b6 arm64: dts: renesas: r9a09g056: Add OSTM0-OSTM7 nodes
694ebe54d549 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable GBETH
4b6db87a7c10 arm64: dts: renesas: r9a09g056: Add GBETH nodes
46869466a047 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable GBETH
7fd2951fbfb5 arm64: dts: renesas: r9a09g057: Add GBETH nodes
d2a7f6061328 arm64: dts: renesas: rzg3e-smarc-som: Enable serial NOR FLASH
ca067cd873d2 arm64: dts: renesas: r9a09g047: Add XSPI node
6afb981042a9 dt-bindings: soc: renesas: Document RZ/V2H EVK board part number
47e339df4236 arm64: dts: qcom: sdm850-lenovo-yoga-c630: enable sensors DSP
3eb07ee1199c arm64: dts: qcom: x1e80100-dell-xps13-9345: Enable fingerprint sensor
2369c0a8d811 spi: spi-fsl-dspi: DSPI support for NXP S32G
519d961ebee1 ARM: dts: bcm958625-meraki-mx6x: Use #pwm-cells = <3>
364569526281 ARM: dts: bcm63178: Add BCMBCA peripherals
a8aa7adbe86e ARM: dts: bcm63148: Add BCMBCA peripherals
72b55d5589da ARM: dts: bcm63138: Add BCMBCA peripherals
40f65eebdc16 ARM: dts: bcm6878: Add BCMBCA peripherals
4db474ab76b1 ARM: dts: bcm6855: Add BCMBCA peripherals
c1fa2261ce24 ARM: dts: bcm6846: Add interrupt to RNG
cfb95bca76c8 dt-bindings: rng: r200: Add interrupt property
8f5c0556e851 ARM: dts: bcm6878: Correct UART0 IRQ number
756cdb1f3650 arm64: dts: broadcom: Add overlay for RP1 device
f3e865c8518c arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
f07526de4e4d arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
82e6696b5c5c arm64: dts: rp1: Add support for RaspberryPi's RP1 device
e4470510ff94 dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
36ec48d1dd05 dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
5bae359ddb89 dt-bindings: clock: Add RaspberryPi RP1 clock bindings
7311a83b9240 ARM64: dts: bcm63158: Add BCMBCA peripherals
c820a00e2552 ARM64: dts: bcm6858: Add BCMBCA peripherals
2a6681b31935 ARM64: dts: bcm6856: Add BCMBCA peripherals
f6d523dc2308 ARM64: dts: bcm4908: Add BCMBCA peripherals
cfb6a63d41fe riscv: dts: spacemit: enable eMMC for K1 SoC
274a9a682e34 dt-bindings: display: convert himax,hx8357d.txt to yaml format
99b29e7ccd61 dt-bindings: display: arm,pl11x: Allow resets property
e13ecc320126 dt-bindings: display: convert sitronix,st7586 to YAML
1e04213799d5 dt-bindings: lcdif: add lcd panel related property for imx28
11b1b6e24edd dt-bindings: soc: Add fsl,imx23-digctl.yaml for i.MX23 and i.MX28
9c5a32bcb7b7 ASoC: Add Richtek RTQ9124 support
d57db601e6b0 ASoC: tas571x: add support for tas5753
caa03026f5ef ASoC: codecs: wcd93xx: Few simplifications of code and
baa572592b2c regulator: dt-bindings: rpi-panel: Add regulator for 7" Raspberry Pi 720x1280
504cdf1cd54f ASoC: dt-bindings: rt9123: Append RTQ9124 description
3174278d792f arm64: dts: rockchip: drop touch panel display from rockpro64
873fbebb9c18 arm64: dts: rockchip: Use standard PHY reset properties for RK3576 ArmSoM Sige5
1222a7f24b9f arm64: dts: rockchip: add ROCK 5T device tree
0f79e5a028f1 arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree
0562055bfc3a arm64: dts: rockchip: rename rk3588-rock-5b.dtsi
9c200495868c dt-bindings: arm: rockchip: add RADXA ROCK 5T
7bcc6969adbc arm64: dts: rockchip: Add spi nodes for RK3528
45b18dd32d6a arm64: dts: rockchip: add DTs for Sakura Pi RK3308B
bfca6dc90f2b dt-bindings: arm: rockchip: Add Sakura Pi RK3308B
6d2e9d5b069d dt-bindings: vendor-prefixes: Add SakuraPi prefix
99295ef16891 arm64: dts: rockchip: Fix cover detection on PineNote
c13e5de9b3a4 arm64: dts: rockchip: Document unused device on i2c1
718ca7a2529e arm64: dts: rockchip: support Ethernet Switch adapter for RK3588 Jaguar
f6310c860d5d arm64: dts: rockchip: Add DSI panel support for gameforce-ace
e53018a1ec5b dt-bindings: iio: adc: adi,ad7606: add gain calibration support
14dc2df77a84 dt-bindings: iio: gyroscope: invensense,itg3200: add binding
2f573d87f578 dt-bindings: iio: adc: st,spear600-adc: txt to yaml format conversion.
ed7d4c99dbc3 dt-bindings: iio: adc: add ad4080
61b12aa8b66f dt-bindings: iio: adc: add ad408x axi variant
05db8b79a0b6 arm64: dts: qcom: sm8750: Trivial stray lines removal
1576a89b79e8 spi: dt-bindings: mxs-spi: allow clocks properpty
feffdd266d46 dt-bindings: spi: dspi: Add S32G support
d87d1c2d9447 dt-bindings: regulator: add pca9450: Add regulator-allowed-modes
fa5cfb1fe890 ASoC: dt-bindings: covert mxs-audio-sgtl5000.txt to yaml format
1a0738c10fdd ASoC: dt-bindings: tas57xx: add tas5753 compatibility
90f889cf60f4 ASoC: dt-bindings: qcom,wcd939x: Document missing VDD_PX supply
36269efd9ee8 dt-bindings: display: himax-hx8394: Add Huiling hl055fhav028c
8cd51ffc1367 dt-bindings: vendor-prefixes: Add prefix for Huiling
534b0f65825d dt-bindings: display: simple: add AUO P238HAN01 panel
158a6f7c3376 Merge drm-next-2025-05-28 into drm-misc-next
af3871ba3627 dt-bindings: allwinner: add H616 DE33 mixer binding
2124a6a99b66 dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support
f5efe4f4902d dt-bindings: display: renesas,rzg2l-du: Add support for RZ/V2H(P) SoC
c625b4924743 dt-bindings: display: panel: Document Renesas R69328 based DSI panel
36ea865fae13 dt-bindings: display: panel: Document Renesas R61307 based DSI panel
0d28beee9809 dt-bindings: display: ti,am65x-dss: Add support for AM62L DSS
a0e2388af079 dt-bindings: gpu: mali-utgard: Add Rockchip RK3528 compatible
ac5d1cdc0275 dt-bindings: display: imx: Add i.MX8qxp Display Controller
963333f8371f dt-bindings: interrupt-controller: Add i.MX8qxp Display Controller interrupt controller
2889c661fb91 dt-bindings: display: imx: Add i.MX8qxp Display Controller command sequencer
57051a9f0a4c dt-bindings: display: imx: Add i.MX8qxp Display Controller AXI performance counter
cf04f0c00267 dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine
0940d6bd8421 dt-bindings: display: imx: Add i.MX8qxp Display Controller display engine
6454e207cfe6 dt-bindings: display: imx: Add i.MX8qxp Display Controller blit engine
8300a1f4ca66 dt-bindings: display: imx: Add i.MX8qxp Display Controller processing units

git-subtree-dir: dts/upstream
git-subtree-split: 4d52919c55f45d027062baf25ebe1c24730699bd

46 files changed, 2619 insertions, 240 deletions

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 897b8135dc1..cb8ce53146f 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -279,8 +279,13 @@
 #define QCOM_ID_QCM8550			604
 #define QCOM_ID_SM8750			618
 #define QCOM_ID_IPQ5300			624
+#define QCOM_ID_SM7635			636
+#define QCOM_ID_SM6650			640
+#define QCOM_ID_SM6650P			641
 #define QCOM_ID_IPQ5321			650
 #define QCOM_ID_IPQ5424			651
+#define QCOM_ID_QCM6690			657
+#define QCOM_ID_QCS6690			658
 #define QCOM_ID_IPQ5404			671
 #define QCOM_ID_QCS9100			667
 #define QCOM_ID_QCS8300			674
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 7ae96c7bd72..f60fff26113 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -122,6 +122,8 @@
 #define ASPEED_RESET_PCIE_DEV_OEN	20
 #define ASPEED_RESET_PCIE_RC_O		19
 #define ASPEED_RESET_PCIE_RC_OEN	18
+#define ASPEED_RESET_MAC2		12
+#define ASPEED_RESET_MAC1		11
 #define ASPEED_RESET_PCI_DP		5
 #define ASPEED_RESET_HACE		4
 #define ASPEED_RESET_AHB		1
diff --git a/include/dt-bindings/clock/cix,sky1.h b/include/dt-bindings/clock/cix,sky1.h
new file mode 100644
index 00000000000..9245ebd1e80
--- /dev/null
+++ b/include/dt-bindings/clock/cix,sky1.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2024-2025 Cix Technology Group Co., Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLK_CIX_SKY1_H
+#define _DT_BINDINGS_CLK_CIX_SKY1_H
+
+#define CLK_TREE_CPU_GICxCLK			0
+#define CLK_TREE_CPU_PPUCLK			1
+#define CLK_TREE_CPU_PERIPHCLK			2
+#define CLK_TREE_DSU_CLK			3
+#define CLK_TREE_DSU_PCLK			4
+#define CLK_TREE_CPU_CLK_BC0			5
+#define CLK_TREE_CPU_CLK_BC1			6
+#define CLK_TREE_CPU_CLK_BC2			7
+#define CLK_TREE_CPU_CLK_BC3			8
+#define CLK_TREE_CPU_CLK_MC0			9
+#define CLK_TREE_CPU_CLK_MC1			10
+#define CLK_TREE_CPU_CLK_MC2			11
+#define CLK_TREE_CPU_CLK_MC3			12
+#define CLK_TREE_CPU_CLK_LC0			13
+#define CLK_TREE_CPU_CLK_LC1			14
+#define CLK_TREE_CPU_CLK_LC2			15
+#define CLK_TREE_CPU_CLK_LC3			16
+#define CLK_TREE_CSI_CTRL0_PCLK			17
+#define CLK_TREE_CSI_CTRL1_PCLK			18
+#define CLK_TREE_CSI_CTRL2_PCLK			19
+#define CLK_TREE_CSI_CTRL3_PCLK			20
+#define CLK_TREE_CSI_DMA0_PCLK			21
+#define CLK_TREE_CSI_DMA1_PCLK			22
+#define CLK_TREE_CSI_DMA2_PCLK			23
+#define CLK_TREE_CSI_DMA3_PCLK			24
+#define CLK_TREE_CSI_PHY0_PSM			25
+#define CLK_TREE_CSI_PHY1_PSM			26
+#define CLK_TREE_CSI_PHY0_APBCLK		27
+#define CLK_TREE_CSI_PHY1_APBCLK		28
+#define CLK_TREE_FCH_APB_CLK			29
+#define CLK_TREE_GPU_CLK_400M			30
+#define CLK_TREE_GPU_CLK_CORE			31
+#define CLK_TREE_GPU_CLK_STACKS			32
+#define CLK_TREE_DP0_PIXEL0			33
+#define CLK_TREE_DP0_PIXEL1			34
+#define CLK_TREE_DP1_PIXEL0			35
+#define CLK_TREE_DP1_PIXEL1			36
+#define CLK_TREE_DP2_PIXEL0			37
+#define CLK_TREE_DP2_PIXEL1			38
+#define CLK_TREE_DP3_PIXEL0			39
+#define CLK_TREE_DP3_PIXEL1			40
+#define CLK_TREE_DP4_PIXEL0			41
+#define CLK_TREE_DP4_PIXEL1			42
+#define CLK_TREE_DPU_CLK			43
+#define CLK_TREE_DPU0_ACLK			44
+#define CLK_TREE_DPU1_ACLK			45
+#define CLK_TREE_DPU2_ACLK			46
+#define CLK_TREE_DPU3_ACLK			47
+#define CLK_TREE_DPU4_ACLK			48
+#define CLK_TREE_DPC0_VIDCLK0			49
+#define CLK_TREE_DPC0_VIDCLK1			50
+#define CLK_TREE_DPC1_VIDCLK0			51
+#define CLK_TREE_DPC1_VIDCLK1			52
+#define CLK_TREE_DPC2_VIDCLK0			53
+#define CLK_TREE_DPC2_VIDCLK1			54
+#define CLK_TREE_DPC3_VIDCLK0			55
+#define CLK_TREE_DPC3_VIDCLK1			56
+#define CLK_TREE_DPC4_VIDCLK0			57
+#define CLK_TREE_DPC4_VIDCLK1			58
+#define CLK_TREE_DPC0_APBCLK			59
+#define CLK_TREE_DPC1_APBCLK			60
+#define CLK_TREE_DPC2_APBCLK			61
+#define CLK_TREE_DPC3_APBCLK			62
+#define CLK_TREE_DPC4_APBCLK			63
+#define CLK_TREE_NPU_MEMCLK			64
+#define CLK_TREE_NPU_SYSCLK			65
+#define CLK_TREE_NPU_DBGCLK			66
+#define CLK_TREE_VPU_APBCLK			67
+#define CLK_TREE_ISP_ACLK			68
+#define CLK_TREE_ISP_SCLK			69
+#define CLK_TREE_AUDIO_CLK4			70
+#define CLK_TREE_AUDIO_CLK5			71
+#define CLK_TREE_CAMERA_MCLK0			72
+#define CLK_TREE_CAMERA_MCLK1			73
+#define CLK_TREE_CAMERA_MCLK2			74
+#define CLK_TREE_CAMERA_MCLK3			75
+#define CLK_TREE_AUDIO_CLK0			76
+#define CLK_TREE_AUDIO_CLK1			77
+#define CLK_TREE_AUDIO_CLK2			78
+#define CLK_TREE_AUDIO_CLK3			79
+#define CLK_TREE_MM_NI700_CLK			80
+#define CLK_TREE_SYS_NI700_CLK			81
+#define CLK_TREE_GMAC0_ACLK			82
+#define CLK_TREE_GMAC1_ACLK			83
+#define CLK_TREE_GMAC0_DIV_ACLK			84
+#define CLK_TREE_GMAC0_DIV_TXCLK		85
+#define CLK_TREE_GMAC0_RGMII0_TXCLK		86
+#define CLK_TREE_GMAC1_DIV_ACLK			87
+#define CLK_TREE_GMAC1_DIV_TXCLK		88
+#define CLK_TREE_GMAC1_RGMII0_TXCLK		89
+#define CLK_TREE_GMAC0_PCLK			90
+#define CLK_TREE_GMAC1_PCLK			91
+#define CLK_TREE_USB2_0_AXI_GATE		92
+#define CLK_TREE_USB2_0_APB_GATE		93
+#define CLK_TREE_USB2_1_AXI_GATE		94
+#define CLK_TREE_USB2_1_APB_GATE		95
+#define CLK_TREE_USB2_2_AXI_GATE		96
+#define CLK_TREE_USB2_2_APB_GATE		97
+#define CLK_TREE_USB2_3_AXI_GATE		98
+#define CLK_TREE_USB2_3_APB_GATE		99
+#define CLK_TREE_USB2_0_PHY_GATE		100
+#define CLK_TREE_USB2_1_PHY_GATE		101
+#define CLK_TREE_USB2_2_PHY_GATE		102
+#define CLK_TREE_USB2_3_PHY_GATE		103
+#define CLK_TREE_USB3C_DRD_AXI_GATE		104
+#define CLK_TREE_USB3C_DRD_APB_GATE		105
+#define CLK_TREE_USB3C_DRD_PHY2_GATE		106
+#define CLK_TREE_USB3C_DRD_PHY3_GATE		107
+#define CLK_TREE_USB3C_0_AXI_GATE		108
+#define CLK_TREE_USB3C_0_APB_GATE		109
+#define CLK_TREE_USB3C_0_PHY2_GATE		110
+#define CLK_TREE_USB3C_0_PHY3_GATE		111
+#define CLK_TREE_USB3C_1_AXI_GATE		112
+#define CLK_TREE_USB3C_1_APB_GATE		113
+#define CLK_TREE_USB3C_1_PHY2_GATE		114
+#define CLK_TREE_USB3C_1_PHY3_GATE		115
+#define CLK_TREE_USB3C_2_AXI_GATE		116
+#define CLK_TREE_USB3C_2_APB_GATE		117
+#define CLK_TREE_USB3C_2_PHY2_GATE		118
+#define CLK_TREE_USB3C_2_PHY3_GATE		119
+#define CLK_TREE_USB3A_0_AXI_GATE		120
+#define CLK_TREE_USB3A_0_APB_GATE		121
+#define CLK_TREE_USB3A_0_PHY2_GATE		122
+#define CLK_TREE_USB3A_1_AXI_GATE		123
+#define CLK_TREE_USB3A_1_APB_GATE		124
+#define CLK_TREE_USB3A_1_PHY2_GATE		125
+#define CLK_TREE_USB3A_PHY3_GATE		126
+#define CLK_TREE_USB2_0_CLK_SOF			127
+#define CLK_TREE_USB2_1_CLK_SOF			128
+#define CLK_TREE_USB2_2_CLK_SOF			129
+#define CLK_TREE_USB2_3_CLK_SOF			130
+#define CLK_TREE_USB3C_DRD_CLK_SOF		131
+#define CLK_TREE_USB3C_H0_CLK_SOF		132
+#define CLK_TREE_USB3C_H1_CLK_SOF		133
+#define CLK_TREE_USB3C_H2_CLK_SOF		134
+#define CLK_TREE_USB3A_H0_CLK_SOF		135
+#define CLK_TREE_USB3A_H1_CLK_SOF		136
+#define CLK_TREE_USB2_0_CLK_LPM			137
+#define CLK_TREE_USB2_1_CLK_LPM			138
+#define CLK_TREE_USB2_2_CLK_LPM			139
+#define CLK_TREE_USB2_3_CLK_LPM			140
+#define CLK_TREE_USB3C_DRD_CLK_LPM		141
+#define CLK_TREE_USB3C_H0_CLK_LPM		142
+#define CLK_TREE_USB3C_H1_CLK_LPM		143
+#define CLK_TREE_USB3C_H2_CLK_LPM		144
+#define CLK_TREE_USB3A_H0_CLK_LPM		145
+#define CLK_TREE_USB3A_H1_CLK_LPM		146
+#define CLK_TREE_USB2_0_PHY_REF			147
+#define CLK_TREE_USB2_1_PHY_REF			148
+#define CLK_TREE_USB2_2_PHY_REF			149
+#define CLK_TREE_USB2_3_PHY_REF			150
+#define CLK_TREE_USB3C_DRD_PHY_REF		151
+#define CLK_TREE_USB3C_H0_PHY_REF		152
+#define CLK_TREE_USB3C_H1_PHY_REF		153
+#define CLK_TREE_USB3C_H2_PHY_REF		154
+#define CLK_TREE_USB3A_H0_PHY_REF		155
+#define CLK_TREE_USB3A_H1_PHY_REF		156
+#define CLK_TREE_USB3C_DRD_PHY_x4_REF		157
+#define CLK_TREE_USB3C_H0_PHY_x4_REF		158
+#define CLK_TREE_USB3C_H1_PHY_x4_REF		159
+#define CLK_TREE_USB3C_H2_PHY_x4_REF		160
+#define CLK_TREE_USB3A_PHY_x2_REF		161
+#define CLK_TREE_PCIE_X8CTRL_APB		162
+#define CLK_TREE_PCIE_X4CTRL_APB		163
+#define CLK_TREE_PCIE_X2CTRL_APB		164
+#define CLK_TREE_PCIE_X1_0CTRL_APB		165
+#define CLK_TREE_PCIE_X1_1CTRL_APB		166
+#define CLK_TREE_PCIE_X8_PHY_APB		167
+#define CLK_TREE_PCIE_X4_PHY_APB		168
+#define CLK_TREE_PCIE_X211_PHY_APB		169
+#define CLK_TREE_PCIE_NI700_CLK			170
+#define CLK_TREE_PCIE_CTRL0_CLK			171
+#define CLK_TREE_PCIE_CTRL1_CLK			172
+#define CLK_TREE_PCIE_CTRL2_CLK			173
+#define CLK_TREE_PCIE_CTRL3_CLK			174
+#define CLK_TREE_PCIE_CTRL4_CLK			175
+#define CLK_TREE_CSI_CTRL0_SYSCLK		176
+#define CLK_TREE_CSI_CTRL1_SYSCLK		177
+#define CLK_TREE_CSI_CTRL2_SYSCLK		178
+#define CLK_TREE_CSI_CTRL3_SYSCLK		179
+#define CLK_TREE_CSI_CTRL0_PIXEL0_CLK		180
+#define CLK_TREE_CSI_CTRL0_PIXEL1_CLK		181
+#define CLK_TREE_CSI_CTRL0_PIXEL2_CLK		182
+#define CLK_TREE_CSI_CTRL0_PIXEL3_CLK		183
+#define CLK_TREE_CSI_CTRL1_PIXEL0_CLK		184
+#define CLK_TREE_CSI_CTRL2_PIXEL0_CLK		185
+#define CLK_TREE_CSI_CTRL2_PIXEL1_CLK		186
+#define CLK_TREE_CSI_CTRL2_PIXEL2_CLK		187
+#define CLK_TREE_CSI_CTRL2_PIXEL3_CLK		188
+#define CLK_TREE_CSI_CTRL3_PIXEL0_CLK		189
+#define CLK_TREE_CI700_GCLK0			190
+#define CLK_TREE_DDRC0_ACLK_CLK			191
+#define CLK_TREE_DDRC1_ACLK_CLK			192
+#define CLK_TREE_DDRC2_ACLK_CLK			193
+#define CLK_TREE_DDRC3_ACLK_CLK			194
+#define CLK_TREE_DDRC0_DFICLK_CLK		195
+#define CLK_TREE_DDRC1_DFICLK_CLK		196
+#define CLK_TREE_DDRC2_DFICLK_CLK		197
+#define CLK_TREE_DDRC3_DFICLK_CLK		198
+#define CLK_TREE_PHY0_SYNC_CLK			199
+#define CLK_TREE_PHY1_SYNC_CLK			200
+#define CLK_TREE_PHY2_SYNC_CLK			201
+#define CLK_TREE_PHY3_SYNC_CLK			202
+#define CLK_TREE_PHY0_BYPASS_CLK		203
+#define CLK_TREE_PHY1_BYPASS_CLK		204
+#define CLK_TREE_PHY2_BYPASS_CLK		205
+#define CLK_TREE_PHY3_BYPASS_CLK		206
+#define CLK_TREE_DDRC_0_APB			207
+#define CLK_TREE_DDRC_1_APB			208
+#define CLK_TREE_DDRC_2_APB			209
+#define CLK_TREE_DDRC_3_APB			210
+#define CLK_TREE_TZC400_0_APB			211
+#define CLK_TREE_TZC400_1_APB			212
+#define CLK_TREE_TZC400_2_APB			213
+#define CLK_TREE_TZC400_3_APB			214
+#define CLK_TREE_S5_SENSOR_HUB_25M		215
+#define CLK_TREE_S5_SENSOR_HUB_400M		216
+#define CLK_TREE_S5_CSS600_100M			217
+#define CLK_TREE_S5_DFD_800M			218
+#define CLK_TREE_S5_CSU_SE_800M			219
+#define CLK_TREE_S5_CSU_PM_800M			220
+#define CLK_TREE_PCIE_REF_B0			221
+#define CLK_TREE_PCIE_REF_B1			222
+#define CLK_TREE_PCIE_REF_B2			223
+#define CLK_TREE_PCIE_REF_B3			224
+#define CLK_TREE_PCIE_REF_B4			225
+#define CLK_TREE_PCIE_REF_PHY_X8		226
+#define CLK_TREE_PCIE_REF_PHY_X4		227
+#define CLK_TREE_PCIE_REF_PHY_X211		228
+#define CLK_TREE_GMAC_REC_CLK			229
+#define CLK_TREE_GPUTOP_PLL			230
+#define CLK_TREE_GPUCORE_PLL			231
+#define CLK_TREE_CPU_PLL_LIT			232
+#define CLK_TREE_CPU_PLL0			233
+#define CLK_TREE_CPU_PLL1			234
+#define CLK_TREE_CPU_PLL2			235
+#define CLK_TREE_CPU_PLL3			236
+#define CLK_TREE_FCH_I3C0_FUNC			237
+#define CLK_TREE_FCH_I3C1_FUNC			238
+#define CLK_TREE_FCH_DMA_ACLK			239
+#define CLK_TREE_FCH_XSPI_FUNC			240
+#define CLK_TREE_FCH_XSPI_MACLK			241
+#define CLK_TREE_FCH_TIMER_FUN			242
+#define CLK_TREE_FCH_APB_IO_S0			243
+#define CLK_TREE_FCH_I3C0_APB			244
+#define CLK_TREE_FCH_I3C1_APB			245
+#define CLK_TREE_FCH_UART0_APB			246
+#define CLK_TREE_FCH_UART1_APB			247
+#define CLK_TREE_FCH_UART2_APB			248
+#define CLK_TREE_FCH_UART3_APB			249
+#define CLK_TREE_FCH_SPI0_APB			250
+#define CLK_TREE_FCH_SPI1_APB			251
+#define CLK_TREE_FCH_XSPI_APB			252
+#define CLK_TREE_FCH_I2C0_APB			253
+#define CLK_TREE_FCH_I2C1_APB			254
+#define CLK_TREE_FCH_I2C2_APB			255
+#define CLK_TREE_FCH_I2C3_APB			256
+#define CLK_TREE_FCH_I2C4_APB			257
+#define CLK_TREE_FCH_I2C5_APB			258
+#define CLK_TREE_FCH_I2C6_APB			259
+#define CLK_TREE_FCH_I2C7_APB			260
+#define CLK_TREE_FCH_TIMER_APB			261
+#define CLK_TREE_FCH_GPIO_APB			262
+#define CLK_TREE_FCH_UART0_FUNC			263
+#define CLK_TREE_FCH_UART1_FUNC			264
+#define CLK_TREE_FCH_UART2_FUNC			265
+#define CLK_TREE_FCH_UART3_FUNC			266
+/* 267~271 not used by AP, skip */
+#define CLK_TREE_GPU_CLK_200M			272
+
+#endif
diff --git a/include/dt-bindings/clock/nvidia,tegra264.h b/include/dt-bindings/clock/nvidia,tegra264.h
new file mode 100644
index 00000000000..0fc2ad5e6ce
--- /dev/null
+++ b/include/dt-bindings/clock/nvidia,tegra264.h
@@ -0,0 +1,466 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H
+#define DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H
+
+#define TEGRA264_CLK_OSC				1
+#define TEGRA264_CLK_CLK_S				2
+#define TEGRA264_CLK_JTAG_REG				3
+#define TEGRA264_CLK_SPLL				4
+#define TEGRA264_CLK_SPLL_OUT0				5
+#define TEGRA264_CLK_SPLL_OUT1				6
+#define TEGRA264_CLK_SPLL_OUT2				7
+#define TEGRA264_CLK_SPLL_OUT3				8
+#define TEGRA264_CLK_SPLL_OUT4				9
+#define TEGRA264_CLK_SPLL_OUT5				10
+#define TEGRA264_CLK_SPLL_OUT6				11
+#define TEGRA264_CLK_SPLL_OUT7				12
+#define TEGRA264_CLK_AON_I2C				13
+#define TEGRA264_CLK_HOST1X				14
+#define TEGRA264_CLK_ISP				15
+#define TEGRA264_CLK_ISP1				16
+#define TEGRA264_CLK_ISP_ROOT				17
+#define TEGRA264_CLK_NAFLL_PVA0_CORE			18
+#define TEGRA264_CLK_NAFLL_PVA0_VPS			19
+#define TEGRA264_CLK_NVCSI				20
+#define TEGRA264_CLK_NVCSILP				21
+#define TEGRA264_CLK_PLLP_OUT0				22
+#define TEGRA264_CLK_PVA0_CPU_AXI			23
+#define TEGRA264_CLK_PVA0_VPS				24
+#define TEGRA264_CLK_PWM10				25
+#define TEGRA264_CLK_PWM2				26
+#define TEGRA264_CLK_PWM3				27
+#define TEGRA264_CLK_PWM4				28
+#define TEGRA264_CLK_PWM5				29
+#define TEGRA264_CLK_PWM9				30
+#define TEGRA264_CLK_QSPI0				31
+#define TEGRA264_CLK_QSPI0_2X_PM			32
+#define TEGRA264_CLK_RCE1_CPU				33
+#define TEGRA264_CLK_RCE1_NIC				34
+#define TEGRA264_CLK_RCE_CPU				35
+#define TEGRA264_CLK_RCE_NIC				36
+#define TEGRA264_CLK_SE					37
+#define TEGRA264_CLK_SEU1				38
+#define TEGRA264_CLK_SEU2				39
+#define TEGRA264_CLK_SEU3				40
+#define TEGRA264_CLK_SE_ROOT				41
+#define TEGRA264_CLK_SPI1				42
+#define TEGRA264_CLK_SPI2				43
+#define TEGRA264_CLK_SPI3				44
+#define TEGRA264_CLK_SPI4				45
+#define TEGRA264_CLK_SPI5				46
+#define TEGRA264_CLK_TOP_I2C				47
+#define TEGRA264_CLK_TSEC				48
+#define TEGRA264_CLK_TSEC_PKA				49
+#define TEGRA264_CLK_UART0				50
+#define TEGRA264_CLK_UART10				51
+#define TEGRA264_CLK_UART11				52
+#define TEGRA264_CLK_UART4				53
+#define TEGRA264_CLK_UART5				54
+#define TEGRA264_CLK_UART8				55
+#define TEGRA264_CLK_UART9				56
+#define TEGRA264_CLK_VI					57
+#define TEGRA264_CLK_VI1				58
+#define TEGRA264_CLK_VIC				59
+#define TEGRA264_CLK_VI_ROOT				60
+#define TEGRA264_CLK_DISPPLL				61
+#define TEGRA264_CLK_SPPLL0				62
+#define TEGRA264_CLK_SPPLL0_CLKOUT1A			63
+#define TEGRA264_CLK_SPPLL0_CLKOUT2A			64
+#define TEGRA264_CLK_SPPLL1				65
+#define TEGRA264_CLK_VPLL0				66
+#define TEGRA264_CLK_VPLL1				67
+#define TEGRA264_CLK_VPLL2				68
+#define TEGRA264_CLK_VPLL3				69
+#define TEGRA264_CLK_VPLL4				70
+#define TEGRA264_CLK_VPLL5				71
+#define TEGRA264_CLK_VPLL6				72
+#define TEGRA264_CLK_VPLL7				73
+#define TEGRA264_CLK_RG0_DIV				74
+#define TEGRA264_CLK_RG1_DIV				75
+#define TEGRA264_CLK_RG2_DIV				76
+#define TEGRA264_CLK_RG3_DIV				77
+#define TEGRA264_CLK_RG4_DIV				78
+#define TEGRA264_CLK_RG5_DIV				79
+#define TEGRA264_CLK_RG6_DIV				80
+#define TEGRA264_CLK_RG7_DIV				81
+#define TEGRA264_CLK_RG0				82
+#define TEGRA264_CLK_RG1				83
+#define TEGRA264_CLK_RG2				84
+#define TEGRA264_CLK_RG3				85
+#define TEGRA264_CLK_RG4				86
+#define TEGRA264_CLK_RG5				87
+#define TEGRA264_CLK_RG6				88
+#define TEGRA264_CLK_RG7				89
+#define TEGRA264_CLK_DISP				90
+#define TEGRA264_CLK_DSC				91
+#define TEGRA264_CLK_DSC_ROOT				92
+#define TEGRA264_CLK_HUB				93
+#define TEGRA264_CLK_VPLLX_SOR0_MUXED			94
+#define TEGRA264_CLK_VPLLX_SOR1_MUXED			95
+#define TEGRA264_CLK_VPLLX_SOR2_MUXED			96
+#define TEGRA264_CLK_VPLLX_SOR3_MUXED			97
+#define TEGRA264_CLK_LINKA_SYM				98
+#define TEGRA264_CLK_LINKB_SYM				99
+#define TEGRA264_CLK_LINKC_SYM				100
+#define TEGRA264_CLK_LINKD_SYM				101
+#define TEGRA264_CLK_PRE_SOR0				102
+#define TEGRA264_CLK_PRE_SOR1				103
+#define TEGRA264_CLK_PRE_SOR2				104
+#define TEGRA264_CLK_PRE_SOR3				105
+#define TEGRA264_CLK_SOR0_PLL_REF			106
+#define TEGRA264_CLK_SOR1_PLL_REF			107
+#define TEGRA264_CLK_SOR2_PLL_REF			108
+#define TEGRA264_CLK_SOR3_PLL_REF			109
+#define TEGRA264_CLK_SOR0_PAD				110
+#define TEGRA264_CLK_SOR1_PAD				111
+#define TEGRA264_CLK_SOR2_PAD				112
+#define TEGRA264_CLK_SOR3_PAD				113
+#define TEGRA264_CLK_SOR0_REF				114
+#define TEGRA264_CLK_SOR1_REF				115
+#define TEGRA264_CLK_SOR2_REF				116
+#define TEGRA264_CLK_SOR3_REF				117
+#define TEGRA264_CLK_SOR0_DIV				118
+#define TEGRA264_CLK_SOR1_DIV				119
+#define TEGRA264_CLK_SOR2_DIV				120
+#define TEGRA264_CLK_SOR3_DIV				121
+#define TEGRA264_CLK_SOR0				122
+#define TEGRA264_CLK_SOR1				123
+#define TEGRA264_CLK_SOR2				124
+#define TEGRA264_CLK_SOR3				125
+#define TEGRA264_CLK_SF0_SOR				126
+#define TEGRA264_CLK_SF1_SOR				127
+#define TEGRA264_CLK_SF2_SOR				128
+#define TEGRA264_CLK_SF3_SOR				129
+#define TEGRA264_CLK_SF4_SOR				130
+#define TEGRA264_CLK_SF5_SOR				131
+#define TEGRA264_CLK_SF6_SOR				132
+#define TEGRA264_CLK_SF7_SOR				133
+#define TEGRA264_CLK_SF0				134
+#define TEGRA264_CLK_SF1				135
+#define TEGRA264_CLK_SF2				136
+#define TEGRA264_CLK_SF3				137
+#define TEGRA264_CLK_SF4				138
+#define TEGRA264_CLK_SF5				139
+#define TEGRA264_CLK_SF6				140
+#define TEGRA264_CLK_SF7				141
+#define TEGRA264_CLK_MAUD				142
+#define TEGRA264_CLK_AZA_2XBIT				143
+#define TEGRA264_CLK_DCE_CPU				144
+#define TEGRA264_CLK_DCE_NIC				145
+#define TEGRA264_CLK_PLLC4				146
+#define TEGRA264_CLK_PLLC4_OUT0				147
+#define TEGRA264_CLK_PLLC4_OUT1				148
+#define TEGRA264_CLK_PLLC4_MUXED			149
+#define TEGRA264_CLK_SDMMC1				150
+#define TEGRA264_CLK_SDMMC_LEGACY_TM			151
+#define TEGRA264_CLK_PLLC0				152
+#define TEGRA264_CLK_NAFLL_BPMP				153
+#define TEGRA264_CLK_PLLP_OUT_PDIV			154
+#define TEGRA264_CLK_DISP_ROOT				155
+#define TEGRA264_CLK_ADSP				156
+#define TEGRA264_CLK_PLLA				157
+#define TEGRA264_CLK_PLLA1				158
+#define TEGRA264_CLK_PLLA1_OUT1				159
+#define TEGRA264_CLK_PLLAON				160
+#define TEGRA264_CLK_PLLAON_APE				161
+#define TEGRA264_CLK_PLLA_OUT0				162
+#define TEGRA264_CLK_AHUB				163
+#define TEGRA264_CLK_APE				164
+#define TEGRA264_CLK_I2S1_SCLK_IN			165
+#define TEGRA264_CLK_I2S2_SCLK_IN			166
+#define TEGRA264_CLK_I2S3_SCLK_IN			167
+#define TEGRA264_CLK_I2S4_SCLK_IN			168
+#define TEGRA264_CLK_I2S5_SCLK_IN			169
+#define TEGRA264_CLK_I2S6_SCLK_IN			170
+#define TEGRA264_CLK_I2S7_SCLK_IN			171
+#define TEGRA264_CLK_I2S8_SCLK_IN			172
+#define TEGRA264_CLK_I2S9_SCLK_IN			173
+#define TEGRA264_CLK_I2S1_AUDIO_SYNC			174
+#define TEGRA264_CLK_I2S2_AUDIO_SYNC			175
+#define TEGRA264_CLK_I2S3_AUDIO_SYNC			176
+#define TEGRA264_CLK_I2S4_AUDIO_SYNC			177
+#define TEGRA264_CLK_I2S5_AUDIO_SYNC			178
+#define TEGRA264_CLK_I2S6_AUDIO_SYNC			179
+#define TEGRA264_CLK_I2S7_AUDIO_SYNC			180
+#define TEGRA264_CLK_I2S8_AUDIO_SYNC			181
+#define TEGRA264_CLK_DMIC1_AUDIO_SYNC			182
+#define TEGRA264_CLK_DSPK1_AUDIO_SYNC			183
+#define TEGRA264_CLK_I2S1				184
+#define TEGRA264_CLK_I2S2				185
+#define TEGRA264_CLK_I2S3				186
+#define TEGRA264_CLK_I2S4				187
+#define TEGRA264_CLK_I2S5				188
+#define TEGRA264_CLK_I2S6				189
+#define TEGRA264_CLK_I2S7				190
+#define TEGRA264_CLK_I2S8				191
+#define TEGRA264_CLK_I2S9				192
+#define TEGRA264_CLK_DMIC1				193
+#define TEGRA264_CLK_DMIC5				194
+#define TEGRA264_CLK_DSPK1				195
+#define TEGRA264_CLK_AON_CPU				196
+#define TEGRA264_CLK_AON_NIC				197
+#define TEGRA264_CLK_BPMP				198
+#define TEGRA264_CLK_AXI_CBB				199
+#define TEGRA264_CLK_FUSE				200
+#define TEGRA264_CLK_TSENSE				201
+#define TEGRA264_CLK_CSITE				202
+#define TEGRA264_CLK_HCSITE				203
+#define TEGRA264_CLK_DBGAPB				204
+#define TEGRA264_CLK_LA					205
+#define TEGRA264_CLK_PLLREFGP				206
+#define TEGRA264_CLK_PLLE0				207
+#define TEGRA264_CLK_UPHY0_PLL0_XDIG			208
+#define TEGRA264_CLK_EQOS_APP				209
+#define TEGRA264_CLK_EQOS_MAC				210
+#define TEGRA264_CLK_EQOS_MACSEC			211
+#define TEGRA264_CLK_EQOS_TX_PCS			212
+#define TEGRA264_CLK_MGBES_PTP_REF			213
+#define TEGRA264_CLK_MGBE0_UPHY1_PLL_XDIG		214
+#define TEGRA264_CLK_MGBE0_TX_PCS			215
+#define TEGRA264_CLK_MGBE0_MAC				216
+#define TEGRA264_CLK_MGBE0_MACSEC			217
+#define TEGRA264_CLK_MGBE0_APP				218
+#define TEGRA264_CLK_MGBE1_UPHY1_PLL_XDIG		219
+#define TEGRA264_CLK_MGBE1_TX_PCS			220
+#define TEGRA264_CLK_MGBE1_MAC				221
+#define TEGRA264_CLK_MGBE1_MACSEC			222
+#define TEGRA264_CLK_MGBE1_APP				223
+#define TEGRA264_CLK_MGBE2_UPHY1_PLL_XDIG		224
+#define TEGRA264_CLK_MGBE2_TX_PCS			225
+#define TEGRA264_CLK_MGBE2_MAC				226
+#define TEGRA264_CLK_MGBE2_MACSEC			227
+#define TEGRA264_CLK_MGBE2_APP				228
+#define TEGRA264_CLK_MGBE3_UPHY1_PLL_XDIG		229
+#define TEGRA264_CLK_MGBE3_TX_PCS			230
+#define TEGRA264_CLK_MGBE3_MAC				231
+#define TEGRA264_CLK_MGBE3_MACSEC			232
+#define TEGRA264_CLK_MGBE3_APP				233
+#define TEGRA264_CLK_PLLREFUFS				234
+#define TEGRA264_CLK_PLLREFUFS_CLKOUT624		235
+#define TEGRA264_CLK_PLLREFUFS_REFCLKOUT		236
+#define TEGRA264_CLK_PLLREFUFS_UFSDEV_REFCLKOUT		237
+#define TEGRA264_CLK_UFSHC_CG_SYS			238
+#define TEGRA264_CLK_MPHY_L0_RX_LS_BIT_DIV		239
+#define TEGRA264_CLK_MPHY_L0_RX_LS_BIT			240
+#define TEGRA264_CLK_MPHY_L0_RX_LS_SYMB_DIV		241
+#define TEGRA264_CLK_MPHY_L0_RX_HS_SYMB_DIV		242
+#define TEGRA264_CLK_MPHY_L0_RX_SYMB			243
+#define TEGRA264_CLK_MPHY_L0_UPHY_TX_FIFO		244
+#define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT_DIV		245
+#define TEGRA264_CLK_MPHY_L0_TX_LS_SYMB_DIV		246
+#define TEGRA264_CLK_UPHY0_PLL4_XDIG			247
+#define TEGRA264_CLK_MPHY_L0_TX_HS_SYMB_DIV		248
+#define TEGRA264_CLK_MPHY_L0_TX_SYMB			249
+#define TEGRA264_CLK_MPHY_L0_TX_LS_3XBIT		250
+#define TEGRA264_CLK_MPHY_L0_RX_ANA			251
+#define TEGRA264_CLK_MPHY_L1_RX_ANA			252
+#define TEGRA264_CLK_MPHY_TX_1MHZ_REF			253
+#define TEGRA264_CLK_MPHY_CORE_PLL_FIXED		254
+#define TEGRA264_CLK_MPHY_IOBIST			255
+#define TEGRA264_CLK_UFSHC_CG_SYS_DIV			256
+#define TEGRA264_CLK_XUSB1_CORE				257
+#define TEGRA264_CLK_XUSB1_FALCON			258
+#define TEGRA264_CLK_XUSB1_FS				259
+#define TEGRA264_CLK_XUSB1_SS				260
+#define TEGRA264_CLK_UPHY0_USB_P0_RX_CORE		261
+#define TEGRA264_CLK_UPHY0_USB_P1_RX_CORE		262
+#define TEGRA264_CLK_UPHY0_USB_P2_RX_CORE		263
+#define TEGRA264_CLK_UPHY0_USB_P3_RX_CORE		264
+#define TEGRA264_CLK_XUSB1_CLK480M_NVWRAP_CORE		265
+#define TEGRA264_CLK_XUSB1_CORE_HOST			266
+#define TEGRA264_CLK_XUSB1_CORE_DEV			267
+#define TEGRA264_CLK_XUSB1_CORE_SUPERSPEED		268
+#define TEGRA264_CLK_XUSB1_FALCON_HOST			269
+#define TEGRA264_CLK_XUSB1_FALCON_SUPERSPEED		270
+#define TEGRA264_CLK_XUSB1_FS_HOST			271
+#define TEGRA264_CLK_XUSB1_FS_DEV			272
+#define TEGRA264_CLK_XUSB1_HS_HSICP			273
+#define TEGRA264_CLK_XUSB1_SS_DEV			274
+#define TEGRA264_CLK_XUSB1_SS_SUPERSPEED		275
+#define TEGRA264_CLK_AON_TOUCH				276
+#define TEGRA264_CLK_AUD_MCLK				277
+#define TEGRA264_CLK_EXTPERIPH1				278
+#define TEGRA264_CLK_EXTPERIPH2				279
+#define TEGRA264_CLK_EXTPERIPH3				280
+#define TEGRA264_CLK_EXTPERIPH4				281
+#define TEGRA264_CLK_JTAG_REG_UNGATED			282
+#define TEGRA264_CLK_IST_BUS				283
+#define TEGRA264_CLK_IST_BUS_RIST_MCC			284
+#define TEGRA264_CLK_MATHS_SEC_RIST			285
+#define TEGRA264_CLK_NAFLL_IST				286
+#define TEGRA264_CLK_RIST_ROOT				287
+#define TEGRA264_CLK_IST_CONTROLLER_RIST		288
+#define TEGRA264_CLK_MSS_ENCRYPT			289
+#define TEGRA264_CLK_EMC				290
+#define TEGRA264_CLK_SPPLL0_CLKOUT100			291
+#define TEGRA264_CLK_SPPLL0_CLKOUT270			292
+#define TEGRA264_CLK_SPPLL1_CLKOUT100			293
+#define TEGRA264_CLK_SPPLL1_CLKOUT270			294
+#define TEGRA264_CLK_DP_LINKA_REF			295
+#define TEGRA264_CLK_DP_LINKB_REF			296
+#define TEGRA264_CLK_DP_LINKC_REF			297
+#define TEGRA264_CLK_DP_LINKD_REF			298
+#define TEGRA264_CLK_PLLNVCSI				299
+#define TEGRA264_CLK_PLLBPMPCAM				300
+#define TEGRA264_CLK_UTMI_PLL1				301
+#define TEGRA264_CLK_UTMI_PLL1_CLKOUT48			302
+#define TEGRA264_CLK_UTMI_PLL1_CLKOUT60			303
+#define TEGRA264_CLK_UTMI_PLL1_CLKOUT480		304
+#define TEGRA264_CLK_NAFLL_ISP				305
+#define TEGRA264_CLK_NAFLL_RCE				306
+#define TEGRA264_CLK_NAFLL_RCE1				307
+#define TEGRA264_CLK_NAFLL_SE				308
+#define TEGRA264_CLK_NAFLL_VI				309
+#define TEGRA264_CLK_NAFLL_VIC				310
+#define TEGRA264_CLK_NAFLL_DCE				311
+#define TEGRA264_CLK_NAFLL_TSEC				312
+#define TEGRA264_CLK_NAFLL_CPAIR0			313
+#define TEGRA264_CLK_NAFLL_CPAIR1			314
+#define TEGRA264_CLK_NAFLL_CPAIR2			315
+#define TEGRA264_CLK_NAFLL_CPAIR3			316
+#define TEGRA264_CLK_NAFLL_CPAIR4			317
+#define TEGRA264_CLK_NAFLL_CPAIR5			318
+#define TEGRA264_CLK_NAFLL_CPAIR6			319
+#define TEGRA264_CLK_NAFLL_GPU_SYS			320
+#define TEGRA264_CLK_NAFLL_GPU_NVD			321
+#define TEGRA264_CLK_NAFLL_GPU_UPROC			322
+#define TEGRA264_CLK_NAFLL_GPU_GPC0			323
+#define TEGRA264_CLK_NAFLL_GPU_GPC1			324
+#define TEGRA264_CLK_NAFLL_GPU_GPC2			325
+#define TEGRA264_CLK_SOR_LINKA_INPUT			326
+#define TEGRA264_CLK_SOR_LINKB_INPUT			327
+#define TEGRA264_CLK_SOR_LINKC_INPUT			328
+#define TEGRA264_CLK_SOR_LINKD_INPUT			329
+#define TEGRA264_CLK_SOR_LINKA_AFIFO			330
+#define TEGRA264_CLK_SOR_LINKB_AFIFO			331
+#define TEGRA264_CLK_SOR_LINKC_AFIFO			332
+#define TEGRA264_CLK_SOR_LINKD_AFIFO			333
+#define TEGRA264_CLK_I2S1_PAD_M				334
+#define TEGRA264_CLK_I2S2_PAD_M				335
+#define TEGRA264_CLK_I2S3_PAD_M				336
+#define TEGRA264_CLK_I2S4_PAD_M				337
+#define TEGRA264_CLK_I2S5_PAD_M				338
+#define TEGRA264_CLK_I2S6_PAD_M				339
+#define TEGRA264_CLK_I2S7_PAD_M				340
+#define TEGRA264_CLK_I2S8_PAD_M				341
+#define TEGRA264_CLK_I2S9_PAD_M				342
+#define TEGRA264_CLK_BPMP_NIC				343
+#define TEGRA264_CLK_CLK1M				344
+#define TEGRA264_CLK_RDET				345
+#define TEGRA264_CLK_ADC_SOC_REF			346
+#define TEGRA264_CLK_UPHY0_PLL0_TXREF			347
+#define TEGRA264_CLK_EQOS_TX				348
+#define TEGRA264_CLK_EQOS_TX_M				349
+#define TEGRA264_CLK_EQOS_RX_PCS_IN			350
+#define TEGRA264_CLK_EQOS_RX_PCS_M			351
+#define TEGRA264_CLK_EQOS_RX_IN				352
+#define TEGRA264_CLK_EQOS_RX				353
+#define TEGRA264_CLK_EQOS_RX_M				354
+#define TEGRA264_CLK_MGBE0_UPHY1_PLL_TXREF		355
+#define TEGRA264_CLK_MGBE0_TX				356
+#define TEGRA264_CLK_MGBE0_TX_M				357
+#define TEGRA264_CLK_MGBE0_RX_PCS_IN			358
+#define TEGRA264_CLK_MGBE0_RX_PCS_M			359
+#define TEGRA264_CLK_MGBE0_RX_IN			360
+#define TEGRA264_CLK_MGBE0_RX_M				361
+#define TEGRA264_CLK_MGBE1_UPHY1_PLL_TXREF		362
+#define TEGRA264_CLK_MGBE1_TX				363
+#define TEGRA264_CLK_MGBE1_TX_M				364
+#define TEGRA264_CLK_MGBE1_RX_PCS_IN			365
+#define TEGRA264_CLK_MGBE1_RX_PCS_M			366
+#define TEGRA264_CLK_MGBE1_RX_IN			367
+#define TEGRA264_CLK_MGBE1_RX_M				368
+#define TEGRA264_CLK_MGBE2_UPHY1_PLL_TXREF		369
+#define TEGRA264_CLK_MGBE2_TX				370
+#define TEGRA264_CLK_MGBE2_TX_M				371
+#define TEGRA264_CLK_MGBE2_RX_PCS_IN			372
+#define TEGRA264_CLK_MGBE2_RX_PCS_M			373
+#define TEGRA264_CLK_MGBE2_RX_IN			374
+#define TEGRA264_CLK_MGBE2_RX_M				375
+#define TEGRA264_CLK_MGBE3_UPHY1_PLL_TXREF		376
+#define TEGRA264_CLK_MGBE3_TX				377
+#define TEGRA264_CLK_MGBE3_TX_M				378
+#define TEGRA264_CLK_MGBE3_RX_PCS_IN			379
+#define TEGRA264_CLK_MGBE3_RX_PCS_M			380
+#define TEGRA264_CLK_MGBE3_RX_IN			381
+#define TEGRA264_CLK_MGBE3_RX_M				382
+#define TEGRA264_CLK_UPHY0_USB_P0_TX_CORE		383
+#define TEGRA264_CLK_UPHY0_USB_P1_TX_CORE		384
+#define TEGRA264_CLK_UPHY0_USB_P2_TX_CORE		385
+#define TEGRA264_CLK_UPHY0_USB_P3_TX_CORE		386
+#define TEGRA264_CLK_UPHY0_USB_P0_TX			387
+#define TEGRA264_CLK_UPHY0_USB_P1_TX			388
+#define TEGRA264_CLK_UPHY0_USB_P2_TX			389
+#define TEGRA264_CLK_UPHY0_USB_P3_TX			390
+#define TEGRA264_CLK_UPHY0_USB_P0_RX_IN			391
+#define TEGRA264_CLK_UPHY0_USB_P1_RX_IN			392
+#define TEGRA264_CLK_UPHY0_USB_P2_RX_IN			393
+#define TEGRA264_CLK_UPHY0_USB_P3_RX_IN			394
+#define TEGRA264_CLK_UPHY0_USB_P0_RX_M			395
+#define TEGRA264_CLK_UPHY0_USB_P1_RX_M			396
+#define TEGRA264_CLK_UPHY0_USB_P2_RX_M			397
+#define TEGRA264_CLK_UPHY0_USB_P3_RX_M			398
+#define TEGRA264_CLK_UPHY0_LANE0_TX_M			399
+#define TEGRA264_CLK_PCIE_C1_XCLK_NOBG_M		400
+#define TEGRA264_CLK_PCIE_C2_XCLK_NOBG_M		401
+#define TEGRA264_CLK_PCIE_C3_XCLK_NOBG_M		402
+#define TEGRA264_CLK_PCIE_C4_XCLK_NOBG_M		403
+#define TEGRA264_CLK_PCIE_C5_XCLK_NOBG_M		404
+#define TEGRA264_CLK_PCIE_C1_L0_RX_M			405
+#define TEGRA264_CLK_PCIE_C1_L1_RX_M			406
+#define TEGRA264_CLK_PCIE_C1_L2_RX_M			407
+#define TEGRA264_CLK_PCIE_C1_L3_RX_M			408
+#define TEGRA264_CLK_PCIE_C2_L0_RX_M			409
+#define TEGRA264_CLK_PCIE_C2_L1_RX_M			410
+#define TEGRA264_CLK_PCIE_C2_L2_RX_M			411
+#define TEGRA264_CLK_PCIE_C2_L3_RX_M			412
+#define TEGRA264_CLK_PCIE_C3_L0_RX_M			413
+#define TEGRA264_CLK_PCIE_C3_L1_RX_M			414
+#define TEGRA264_CLK_PCIE_C4_L0_RX_M			415
+#define TEGRA264_CLK_PCIE_C4_L1_RX_M			416
+#define TEGRA264_CLK_PCIE_C4_L2_RX_M			417
+#define TEGRA264_CLK_PCIE_C4_L3_RX_M			418
+#define TEGRA264_CLK_PCIE_C4_L4_RX_M			419
+#define TEGRA264_CLK_PCIE_C4_L5_RX_M			420
+#define TEGRA264_CLK_PCIE_C4_L6_RX_M			421
+#define TEGRA264_CLK_PCIE_C4_L7_RX_M			422
+#define TEGRA264_CLK_PCIE_C5_L0_RX_M			423
+#define TEGRA264_CLK_PCIE_C5_L1_RX_M			424
+#define TEGRA264_CLK_PCIE_C5_L2_RX_M			425
+#define TEGRA264_CLK_PCIE_C5_L3_RX_M			426
+#define TEGRA264_CLK_MPHY_L0_RX_PWM_BIT_M		427
+#define TEGRA264_CLK_MPHY_L1_RX_PWM_BIT_M		428
+#define TEGRA264_CLK_DBB_UPHY0				429
+#define TEGRA264_CLK_UPHY0_UXL_CORE			430
+#define TEGRA264_CLK_ISC_CPU_ROOT			431
+#define TEGRA264_CLK_ISC_NIC				432
+#define TEGRA264_CLK_CTC_TXCLK0_M			433
+#define TEGRA264_CLK_CTC_TXCLK1_M			434
+#define TEGRA264_CLK_CTC_RXCLK0_M			435
+#define TEGRA264_CLK_CTC_RXCLK1_M			436
+#define TEGRA264_CLK_PLLREFGP_OUT			437
+#define TEGRA264_CLK_PLLREFGP_OUT1			438
+#define TEGRA264_CLK_GPU_SYS				439
+#define TEGRA264_CLK_GPU_NVD				440
+#define TEGRA264_CLK_GPU_UPROC				441
+#define TEGRA264_CLK_GPU_GPC0				442
+#define TEGRA264_CLK_GPU_GPC1				443
+#define TEGRA264_CLK_GPU_GPC2				444
+#define TEGRA264_CLK_PLLX				445
+#define TEGRA264_CLK_APE_SOUNDWIRE_MSRC0		446
+#define TEGRA264_CLK_APE_SOUNDWIRE_DATA_EN_SHAPER	447
+#define TEGRA264_CLK_AO_SOUNDWIRE_MSRC0			448
+#define TEGRA264_CLK_AO_SOUNDWIRE_DATA_EN_SHAPER	449
+#define TEGRA264_CLK_MGBE0_TX_SER			459
+#define TEGRA264_CLK_MGBE1_TX_SER			460
+#define TEGRA264_CLK_MGBE2_TX_SER			461
+#define TEGRA264_CLK_MGBE3_TX_SER			462
+#define TEGRA264_CLK_MGBE0_RX_SER			463
+#define TEGRA264_CLK_MGBE1_RX_SER			464
+#define TEGRA264_CLK_MGBE2_RX_SER			465
+#define TEGRA264_CLK_MGBE3_RX_SER			466
+#define TEGRA264_CLK_DPAUX				467
+
+#endif /* DT_BINDINGS_CLOCK_NVIDIA_TEGRA264_H */
diff --git a/include/dt-bindings/clock/nxp,imx94-clock.h b/include/dt-bindings/clock/nxp,imx94-clock.h
new file mode 100644
index 00000000000..c4ba13352b9
--- /dev/null
+++ b/include/dt-bindings/clock/nxp,imx94-clock.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX94_H
+#define __DT_BINDINGS_CLOCK_IMX94_H
+
+#define IMX94_CLK_DISPMIX_CLK_SEL	0
+
+#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE	0
+
+#endif /* __DT_BINDINGS_CLOCK_IMX94_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
index e364006aa6e..b9d8438a15f 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
@@ -249,6 +249,16 @@
 #define GCC_UFS_MEM_CLKREF_EN					239
 #define GCC_UFS_CARD_CLKREF_EN					240
 #define GPLL9							241
+#define GCC_CAMERA_AHB_CLK					242
+#define GCC_CAMERA_XO_CLK					243
+#define GCC_CPUSS_DVM_BUS_CLK					244
+#define GCC_CPUSS_GNOC_CLK					245
+#define GCC_DISP_AHB_CLK					246
+#define GCC_DISP_XO_CLK						247
+#define GCC_GPU_CFG_AHB_CLK					248
+#define GCC_NPU_CFG_AHB_CLK					249
+#define GCC_VIDEO_AHB_CLK					250
+#define GCC_VIDEO_XO_CLK					251
 
 #define GCC_EMAC_BCR						0
 #define GCC_GPU_BCR						1
diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
new file mode 100644
index 00000000000..586d1c9b33b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ5018_CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ5018. */
+#define IPQ5018_XO_24MHZ_CLK			1
+#define IPQ5018_SLEEP_32KHZ_CLK			2
+#define IPQ5018_ETH_50MHZ_CLK			3
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
new file mode 100644
index 00000000000..f643c2668c0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ5424_CMN_PLL_CLK			0
+
+/* The output clocks from CMN PLL of IPQ5424. */
+#define IPQ5424_XO_24MHZ_CLK			1
+#define IPQ5424_SLEEP_32KHZ_CLK			2
+#define IPQ5424_PCS_31P25MHZ_CLK		3
+#define IPQ5424_NSS_300MHZ_CLK			4
+#define IPQ5424_PPE_375MHZ_CLK			5
+#define IPQ5424_ETH0_50MHZ_CLK			6
+#define IPQ5424_ETH1_50MHZ_CLK			7
+#define IPQ5424_ETH2_50MHZ_CLK			8
+#define IPQ5424_ETH_25MHZ_CLK			9
+#endif
diff --git a/include/dt-bindings/clock/qcom,milos-camcc.h b/include/dt-bindings/clock/qcom,milos-camcc.h
new file mode 100644
index 00000000000..21925dca9a2
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-camcc.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_MILOS_H
+
+/* CAM_CC clocks */
+#define CAM_CC_PLL0						0
+#define CAM_CC_PLL0_OUT_EVEN					1
+#define CAM_CC_PLL0_OUT_ODD					2
+#define CAM_CC_PLL1						3
+#define CAM_CC_PLL1_OUT_EVEN					4
+#define CAM_CC_PLL2						5
+#define CAM_CC_PLL2_OUT_EVEN					6
+#define CAM_CC_PLL3						7
+#define CAM_CC_PLL3_OUT_EVEN					8
+#define CAM_CC_PLL4						9
+#define CAM_CC_PLL4_OUT_EVEN					10
+#define CAM_CC_PLL5						11
+#define CAM_CC_PLL5_OUT_EVEN					12
+#define CAM_CC_PLL6						13
+#define CAM_CC_PLL6_OUT_EVEN					14
+#define CAM_CC_BPS_AHB_CLK					15
+#define CAM_CC_BPS_AREG_CLK					16
+#define CAM_CC_BPS_CLK						17
+#define CAM_CC_BPS_CLK_SRC					18
+#define CAM_CC_CAMNOC_ATB_CLK					19
+#define CAM_CC_CAMNOC_AXI_CLK_SRC				20
+#define CAM_CC_CAMNOC_AXI_HF_CLK				21
+#define CAM_CC_CAMNOC_AXI_SF_CLK				22
+#define CAM_CC_CAMNOC_NRT_AXI_CLK				23
+#define CAM_CC_CAMNOC_RT_AXI_CLK				24
+#define CAM_CC_CCI_0_CLK					25
+#define CAM_CC_CCI_0_CLK_SRC					26
+#define CAM_CC_CCI_1_CLK					27
+#define CAM_CC_CCI_1_CLK_SRC					28
+#define CAM_CC_CORE_AHB_CLK					29
+#define CAM_CC_CPAS_AHB_CLK					30
+#define CAM_CC_CPHY_RX_CLK_SRC					31
+#define CAM_CC_CRE_AHB_CLK					32
+#define CAM_CC_CRE_CLK						33
+#define CAM_CC_CRE_CLK_SRC					34
+#define CAM_CC_CSI0PHYTIMER_CLK					35
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				36
+#define CAM_CC_CSI1PHYTIMER_CLK					37
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				38
+#define CAM_CC_CSI2PHYTIMER_CLK					39
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				40
+#define CAM_CC_CSI3PHYTIMER_CLK					41
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				42
+#define CAM_CC_CSIPHY0_CLK					43
+#define CAM_CC_CSIPHY1_CLK					44
+#define CAM_CC_CSIPHY2_CLK					45
+#define CAM_CC_CSIPHY3_CLK					46
+#define CAM_CC_FAST_AHB_CLK_SRC					47
+#define CAM_CC_GDSC_CLK						48
+#define CAM_CC_ICP_ATB_CLK					49
+#define CAM_CC_ICP_CLK						50
+#define CAM_CC_ICP_CLK_SRC					51
+#define CAM_CC_ICP_CTI_CLK					52
+#define CAM_CC_ICP_TS_CLK					53
+#define CAM_CC_MCLK0_CLK					54
+#define CAM_CC_MCLK0_CLK_SRC					55
+#define CAM_CC_MCLK1_CLK					56
+#define CAM_CC_MCLK1_CLK_SRC					57
+#define CAM_CC_MCLK2_CLK					58
+#define CAM_CC_MCLK2_CLK_SRC					59
+#define CAM_CC_MCLK3_CLK					60
+#define CAM_CC_MCLK3_CLK_SRC					61
+#define CAM_CC_MCLK4_CLK					62
+#define CAM_CC_MCLK4_CLK_SRC					63
+#define CAM_CC_OPE_0_AHB_CLK					64
+#define CAM_CC_OPE_0_AREG_CLK					65
+#define CAM_CC_OPE_0_CLK					66
+#define CAM_CC_OPE_0_CLK_SRC					67
+#define CAM_CC_SLEEP_CLK					68
+#define CAM_CC_SLEEP_CLK_SRC					69
+#define CAM_CC_SLOW_AHB_CLK_SRC					70
+#define CAM_CC_SOC_AHB_CLK					71
+#define CAM_CC_SYS_TMR_CLK					72
+#define CAM_CC_TFE_0_AHB_CLK					73
+#define CAM_CC_TFE_0_CLK					74
+#define CAM_CC_TFE_0_CLK_SRC					75
+#define CAM_CC_TFE_0_CPHY_RX_CLK				76
+#define CAM_CC_TFE_0_CSID_CLK					77
+#define CAM_CC_TFE_0_CSID_CLK_SRC				78
+#define CAM_CC_TFE_1_AHB_CLK					79
+#define CAM_CC_TFE_1_CLK					80
+#define CAM_CC_TFE_1_CLK_SRC					81
+#define CAM_CC_TFE_1_CPHY_RX_CLK				82
+#define CAM_CC_TFE_1_CSID_CLK					83
+#define CAM_CC_TFE_1_CSID_CLK_SRC				84
+#define CAM_CC_TFE_2_AHB_CLK					85
+#define CAM_CC_TFE_2_CLK					86
+#define CAM_CC_TFE_2_CLK_SRC					87
+#define CAM_CC_TFE_2_CPHY_RX_CLK				88
+#define CAM_CC_TFE_2_CSID_CLK					89
+#define CAM_CC_TFE_2_CSID_CLK_SRC				90
+#define CAM_CC_TOP_SHIFT_CLK					91
+#define CAM_CC_XO_CLK_SRC					92
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR						0
+#define CAM_CC_CAMNOC_BCR					1
+#define CAM_CC_CAMSS_TOP_BCR					2
+#define CAM_CC_CCI_0_BCR					3
+#define CAM_CC_CCI_1_BCR					4
+#define CAM_CC_CPAS_BCR						5
+#define CAM_CC_CRE_BCR						6
+#define CAM_CC_CSI0PHY_BCR					7
+#define CAM_CC_CSI1PHY_BCR					8
+#define CAM_CC_CSI2PHY_BCR					9
+#define CAM_CC_CSI3PHY_BCR					10
+#define CAM_CC_ICP_BCR						11
+#define CAM_CC_MCLK0_BCR					12
+#define CAM_CC_MCLK1_BCR					13
+#define CAM_CC_MCLK2_BCR					14
+#define CAM_CC_MCLK3_BCR					15
+#define CAM_CC_MCLK4_BCR					16
+#define CAM_CC_OPE_0_BCR					17
+#define CAM_CC_TFE_0_BCR					18
+#define CAM_CC_TFE_1_BCR					19
+#define CAM_CC_TFE_2_BCR					20
+
+/* CAM_CC power domains */
+#define CAM_CC_CAMSS_TOP_GDSC					0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,milos-dispcc.h b/include/dt-bindings/clock/qcom,milos-dispcc.h
new file mode 100644
index 00000000000..c70f23f32f0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-dispcc.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0						0
+#define DISP_CC_MDSS_ACCU_CLK					1
+#define DISP_CC_MDSS_AHB1_CLK					2
+#define DISP_CC_MDSS_AHB_CLK					3
+#define DISP_CC_MDSS_AHB_CLK_SRC				4
+#define DISP_CC_MDSS_BYTE0_CLK					5
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				6
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				7
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				8
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				9
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				10
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				11
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				12
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				13
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			14
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			15
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				16
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			17
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				18
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			19
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		20
+#define DISP_CC_MDSS_ESC0_CLK					21
+#define DISP_CC_MDSS_ESC0_CLK_SRC				22
+#define DISP_CC_MDSS_MDP1_CLK					23
+#define DISP_CC_MDSS_MDP_CLK					24
+#define DISP_CC_MDSS_MDP_CLK_SRC				25
+#define DISP_CC_MDSS_MDP_LUT1_CLK				26
+#define DISP_CC_MDSS_MDP_LUT_CLK				27
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				28
+#define DISP_CC_MDSS_PCLK0_CLK					29
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				30
+#define DISP_CC_MDSS_RSCC_AHB_CLK				31
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				32
+#define DISP_CC_MDSS_VSYNC1_CLK					33
+#define DISP_CC_MDSS_VSYNC_CLK					34
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				35
+#define DISP_CC_SLEEP_CLK					36
+#define DISP_CC_SLEEP_CLK_SRC					37
+#define DISP_CC_XO_CLK						38
+#define DISP_CC_XO_CLK_SRC					39
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC					0
+#define DISP_CC_MDSS_CORE_INT2_GDSC				1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,milos-gcc.h b/include/dt-bindings/clock/qcom,milos-gcc.h
new file mode 100644
index 00000000000..a530ca39e1e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-gcc.h
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_MILOS_H
+
+/* GCC clocks */
+#define GCC_GPLL0						0
+#define GCC_GPLL0_OUT_EVEN					1
+#define GCC_GPLL2						2
+#define GCC_GPLL4						3
+#define GCC_GPLL6						4
+#define GCC_GPLL7						5
+#define GCC_GPLL9						6
+#define GCC_AGGRE_NOC_PCIE_AXI_CLK				7
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				8
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			9
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				10
+#define GCC_BOOT_ROM_AHB_CLK					11
+#define GCC_CAMERA_AHB_CLK					12
+#define GCC_CAMERA_HF_AXI_CLK					13
+#define GCC_CAMERA_HF_XO_CLK					14
+#define GCC_CAMERA_SF_AXI_CLK					15
+#define GCC_CAMERA_SF_XO_CLK					16
+#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK				17
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				18
+#define GCC_CNOC_PCIE_SF_AXI_CLK				19
+#define GCC_DDRSS_GPU_AXI_CLK					20
+#define GCC_DDRSS_PCIE_SF_QTB_CLK				21
+#define GCC_DISP_AHB_CLK					22
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				23
+#define GCC_DISP_HF_AXI_CLK					24
+#define GCC_DISP_XO_CLK						25
+#define GCC_GP1_CLK						26
+#define GCC_GP1_CLK_SRC						27
+#define GCC_GP2_CLK						28
+#define GCC_GP2_CLK_SRC						29
+#define GCC_GP3_CLK						30
+#define GCC_GP3_CLK_SRC						31
+#define GCC_GPU_CFG_AHB_CLK					32
+#define GCC_GPU_GPLL0_CLK_SRC					33
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				34
+#define GCC_GPU_MEMNOC_GFX_CLK					35
+#define GCC_GPU_SNOC_DVM_GFX_CLK				36
+#define GCC_PCIE_0_AUX_CLK					37
+#define GCC_PCIE_0_AUX_CLK_SRC					38
+#define GCC_PCIE_0_CFG_AHB_CLK					39
+#define GCC_PCIE_0_MSTR_AXI_CLK					40
+#define GCC_PCIE_0_PHY_RCHNG_CLK				41
+#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC				42
+#define GCC_PCIE_0_PIPE_CLK					43
+#define GCC_PCIE_0_PIPE_CLK_SRC					44
+#define GCC_PCIE_0_PIPE_DIV2_CLK				45
+#define GCC_PCIE_0_PIPE_DIV2_CLK_SRC				46
+#define GCC_PCIE_0_SLV_AXI_CLK					47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48
+#define GCC_PCIE_1_AUX_CLK					49
+#define GCC_PCIE_1_AUX_CLK_SRC					50
+#define GCC_PCIE_1_CFG_AHB_CLK					51
+#define GCC_PCIE_1_MSTR_AXI_CLK					52
+#define GCC_PCIE_1_PHY_RCHNG_CLK				53
+#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC				54
+#define GCC_PCIE_1_PIPE_CLK					55
+#define GCC_PCIE_1_PIPE_CLK_SRC					56
+#define GCC_PCIE_1_PIPE_DIV2_CLK				57
+#define GCC_PCIE_1_PIPE_DIV2_CLK_SRC				58
+#define GCC_PCIE_1_SLV_AXI_CLK					59
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				60
+#define GCC_PCIE_RSCC_CFG_AHB_CLK				61
+#define GCC_PCIE_RSCC_XO_CLK					62
+#define GCC_PDM2_CLK						63
+#define GCC_PDM2_CLK_SRC					64
+#define GCC_PDM_AHB_CLK						65
+#define GCC_PDM_XO4_CLK						66
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				67
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				68
+#define GCC_QMIP_DISP_AHB_CLK					69
+#define GCC_QMIP_GPU_AHB_CLK					70
+#define GCC_QMIP_PCIE_AHB_CLK					71
+#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK				72
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK				73
+#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK				74
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				75
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				76
+#define GCC_QUPV3_WRAP0_CORE_CLK				77
+#define GCC_QUPV3_WRAP0_QSPI_REF_CLK				78
+#define GCC_QUPV3_WRAP0_QSPI_REF_CLK_SRC			79
+#define GCC_QUPV3_WRAP0_S0_CLK					80
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				81
+#define GCC_QUPV3_WRAP0_S1_CLK					82
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				83
+#define GCC_QUPV3_WRAP0_S2_CLK					84
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				85
+#define GCC_QUPV3_WRAP0_S3_CLK					86
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				87
+#define GCC_QUPV3_WRAP0_S4_CLK					88
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				89
+#define GCC_QUPV3_WRAP0_S5_CLK					90
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				91
+#define GCC_QUPV3_WRAP0_S6_CLK					92
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				93
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK				94
+#define GCC_QUPV3_WRAP1_CORE_CLK				95
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK				96
+#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC			97
+#define GCC_QUPV3_WRAP1_S0_CLK					98
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				99
+#define GCC_QUPV3_WRAP1_S1_CLK					100
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				101
+#define GCC_QUPV3_WRAP1_S2_CLK					102
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				103
+#define GCC_QUPV3_WRAP1_S3_CLK					104
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				105
+#define GCC_QUPV3_WRAP1_S4_CLK					106
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				107
+#define GCC_QUPV3_WRAP1_S5_CLK					108
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				109
+#define GCC_QUPV3_WRAP1_S6_CLK					110
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				111
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				112
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				113
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				114
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				115
+#define GCC_SDCC1_AHB_CLK					116
+#define GCC_SDCC1_APPS_CLK					117
+#define GCC_SDCC1_APPS_CLK_SRC					118
+#define GCC_SDCC1_ICE_CORE_CLK					119
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				120
+#define GCC_SDCC2_AHB_CLK					121
+#define GCC_SDCC2_APPS_CLK					122
+#define GCC_SDCC2_APPS_CLK_SRC					123
+#define GCC_UFS_PHY_AHB_CLK					124
+#define GCC_UFS_PHY_AXI_CLK					125
+#define GCC_UFS_PHY_AXI_CLK_SRC					126
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK				127
+#define GCC_UFS_PHY_ICE_CORE_CLK				128
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				129
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				130
+#define GCC_UFS_PHY_PHY_AUX_CLK					131
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				132
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				133
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				134
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				135
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				138
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				140
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				141
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			142
+#define GCC_USB30_PRIM_ATB_CLK					143
+#define GCC_USB30_PRIM_MASTER_CLK				144
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				145
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				146
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			147
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		148
+#define GCC_USB30_PRIM_SLEEP_CLK				149
+#define GCC_USB3_PRIM_PHY_AUX_CLK				150
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				151
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				152
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				153
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC				154
+#define GCC_VIDEO_AHB_CLK					155
+#define GCC_VIDEO_AXI0_CLK					156
+#define GCC_VIDEO_XO_CLK					157
+
+/* GCC resets */
+#define GCC_CAMERA_BCR						0
+#define GCC_DISPLAY_BCR						1
+#define GCC_GPU_BCR						2
+#define GCC_PCIE_0_BCR						3
+#define GCC_PCIE_0_LINK_DOWN_BCR				4
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR				5
+#define GCC_PCIE_0_PHY_BCR					6
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR			7
+#define GCC_PCIE_1_BCR						8
+#define GCC_PCIE_1_LINK_DOWN_BCR				9
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR				10
+#define GCC_PCIE_1_PHY_BCR					11
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR			12
+#define GCC_PCIE_RSCC_BCR					13
+#define GCC_PDM_BCR						14
+#define GCC_QUPV3_WRAPPER_0_BCR					15
+#define GCC_QUPV3_WRAPPER_1_BCR					16
+#define GCC_QUSB2PHY_PRIM_BCR					17
+#define GCC_QUSB2PHY_SEC_BCR					18
+#define GCC_SDCC1_BCR						19
+#define GCC_SDCC2_BCR						20
+#define GCC_UFS_PHY_BCR						21
+#define GCC_USB30_PRIM_BCR					22
+#define GCC_USB3_DP_PHY_PRIM_BCR				23
+#define GCC_USB3_PHY_PRIM_BCR					24
+#define GCC_USB3PHY_PHY_PRIM_BCR				25
+#define GCC_VIDEO_AXI0_CLK_ARES					26
+#define GCC_VIDEO_BCR						27
+
+/* GCC power domains */
+#define PCIE_0_GDSC						0
+#define PCIE_0_PHY_GDSC						1
+#define PCIE_1_GDSC						2
+#define PCIE_1_PHY_GDSC						3
+#define UFS_PHY_GDSC						4
+#define UFS_MEM_PHY_GDSC					5
+#define USB30_PRIM_GDSC						6
+#define USB3_PHY_GDSC						7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,milos-gpucc.h b/include/dt-bindings/clock/qcom,milos-gpucc.h
new file mode 100644
index 00000000000..6ff1925d409
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-gpucc.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_MILOS_H
+
+/* GPU_CC clocks */
+#define GPU_CC_PLL0						0
+#define GPU_CC_PLL0_OUT_EVEN					1
+#define GPU_CC_AHB_CLK						2
+#define GPU_CC_CB_CLK						3
+#define GPU_CC_CX_ACCU_SHIFT_CLK				4
+#define GPU_CC_CX_FF_CLK					5
+#define GPU_CC_CX_GMU_CLK					6
+#define GPU_CC_CXO_AON_CLK					7
+#define GPU_CC_CXO_CLK						8
+#define GPU_CC_DEMET_CLK					9
+#define GPU_CC_DEMET_DIV_CLK_SRC				10
+#define GPU_CC_DPM_CLK						11
+#define GPU_CC_FF_CLK_SRC					12
+#define GPU_CC_FREQ_MEASURE_CLK					13
+#define GPU_CC_GMU_CLK_SRC					14
+#define GPU_CC_GX_ACCU_SHIFT_CLK				15
+#define GPU_CC_GX_ACD_AHB_FF_CLK				16
+#define GPU_CC_GX_AHB_FF_CLK					17
+#define GPU_CC_GX_GMU_CLK					18
+#define GPU_CC_GX_RCG_AHB_FF_CLK				19
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				20
+#define GPU_CC_HUB_AON_CLK					21
+#define GPU_CC_HUB_CLK_SRC					22
+#define GPU_CC_HUB_CX_INT_CLK					23
+#define GPU_CC_HUB_DIV_CLK_SRC					24
+#define GPU_CC_MEMNOC_GFX_CLK					25
+#define GPU_CC_RSCC_HUB_AON_CLK					26
+#define GPU_CC_RSCC_XO_AON_CLK					27
+#define GPU_CC_SLEEP_CLK					28
+#define GPU_CC_XO_CLK_SRC					29
+#define GPU_CC_XO_DIV_CLK_SRC					30
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR						0
+#define GPU_CC_CX_BCR						1
+#define GPU_CC_FAST_HUB_BCR					2
+#define GPU_CC_FF_BCR						3
+#define GPU_CC_GMU_BCR						4
+#define GPU_CC_GX_BCR						5
+#define GPU_CC_RBCPR_BCR					6
+#define GPU_CC_XO_BCR						7
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC						0
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,milos-videocc.h b/include/dt-bindings/clock/qcom,milos-videocc.h
new file mode 100644
index 00000000000..3544db81ffa
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,milos-videocc.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MILOS_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_PLL0						0
+#define VIDEO_CC_AHB_CLK					1
+#define VIDEO_CC_AHB_CLK_SRC					2
+#define VIDEO_CC_MVS0_CLK					3
+#define VIDEO_CC_MVS0_CLK_SRC					4
+#define VIDEO_CC_MVS0_DIV_CLK_SRC				5
+#define VIDEO_CC_MVS0_SHIFT_CLK					6
+#define VIDEO_CC_MVS0C_CLK					7
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC				8
+#define VIDEO_CC_MVS0C_SHIFT_CLK				9
+#define VIDEO_CC_SLEEP_CLK					10
+#define VIDEO_CC_SLEEP_CLK_SRC					11
+#define VIDEO_CC_XO_CLK						12
+#define VIDEO_CC_XO_CLK_SRC					13
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_MVS0_BCR					1
+#define VIDEO_CC_MVS0C_CLK_ARES					2
+#define VIDEO_CC_MVS0C_BCR					3
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC					0
+#define VIDEO_CC_MVS0C_GDSC					1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,qcs615-camcc.h b/include/dt-bindings/clock/qcom,qcs615-camcc.h
new file mode 100644
index 00000000000..aec57dddc06
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-camcc.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_QCS615_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK					0
+#define CAM_CC_BPS_AREG_CLK					1
+#define CAM_CC_BPS_AXI_CLK					2
+#define CAM_CC_BPS_CLK						3
+#define CAM_CC_BPS_CLK_SRC					4
+#define CAM_CC_CAMNOC_ATB_CLK					5
+#define CAM_CC_CAMNOC_AXI_CLK					6
+#define CAM_CC_CCI_CLK						7
+#define CAM_CC_CCI_CLK_SRC					8
+#define CAM_CC_CORE_AHB_CLK					9
+#define CAM_CC_CPAS_AHB_CLK					10
+#define CAM_CC_CPHY_RX_CLK_SRC					11
+#define CAM_CC_CSI0PHYTIMER_CLK					12
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				13
+#define CAM_CC_CSI1PHYTIMER_CLK					14
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				15
+#define CAM_CC_CSI2PHYTIMER_CLK					16
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				17
+#define CAM_CC_CSIPHY0_CLK					18
+#define CAM_CC_CSIPHY1_CLK					19
+#define CAM_CC_CSIPHY2_CLK					20
+#define CAM_CC_FAST_AHB_CLK_SRC					21
+#define CAM_CC_ICP_ATB_CLK					22
+#define CAM_CC_ICP_CLK						23
+#define CAM_CC_ICP_CLK_SRC					24
+#define CAM_CC_ICP_CTI_CLK					25
+#define CAM_CC_ICP_TS_CLK					26
+#define CAM_CC_IFE_0_AXI_CLK					27
+#define CAM_CC_IFE_0_CLK					28
+#define CAM_CC_IFE_0_CLK_SRC					29
+#define CAM_CC_IFE_0_CPHY_RX_CLK				30
+#define CAM_CC_IFE_0_CSID_CLK					31
+#define CAM_CC_IFE_0_CSID_CLK_SRC				32
+#define CAM_CC_IFE_0_DSP_CLK					33
+#define CAM_CC_IFE_1_AXI_CLK					34
+#define CAM_CC_IFE_1_CLK					35
+#define CAM_CC_IFE_1_CLK_SRC					36
+#define CAM_CC_IFE_1_CPHY_RX_CLK				37
+#define CAM_CC_IFE_1_CSID_CLK					38
+#define CAM_CC_IFE_1_CSID_CLK_SRC				39
+#define CAM_CC_IFE_1_DSP_CLK					40
+#define CAM_CC_IFE_LITE_CLK					41
+#define CAM_CC_IFE_LITE_CLK_SRC					42
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK				43
+#define CAM_CC_IFE_LITE_CSID_CLK				44
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC				45
+#define CAM_CC_IPE_0_AHB_CLK					46
+#define CAM_CC_IPE_0_AREG_CLK					47
+#define CAM_CC_IPE_0_AXI_CLK					48
+#define CAM_CC_IPE_0_CLK					49
+#define CAM_CC_IPE_0_CLK_SRC					50
+#define CAM_CC_JPEG_CLK						51
+#define CAM_CC_JPEG_CLK_SRC					52
+#define CAM_CC_LRME_CLK						53
+#define CAM_CC_LRME_CLK_SRC					54
+#define CAM_CC_MCLK0_CLK					55
+#define CAM_CC_MCLK0_CLK_SRC					56
+#define CAM_CC_MCLK1_CLK					57
+#define CAM_CC_MCLK1_CLK_SRC					58
+#define CAM_CC_MCLK2_CLK					59
+#define CAM_CC_MCLK2_CLK_SRC					60
+#define CAM_CC_MCLK3_CLK					61
+#define CAM_CC_MCLK3_CLK_SRC					62
+#define CAM_CC_PLL0						63
+#define CAM_CC_PLL1						64
+#define CAM_CC_PLL2						65
+#define CAM_CC_PLL2_OUT_AUX2					66
+#define CAM_CC_PLL3						67
+#define CAM_CC_SLOW_AHB_CLK_SRC					68
+#define CAM_CC_SOC_AHB_CLK					69
+#define CAM_CC_SYS_TMR_CLK					70
+
+/* CAM_CC power domains */
+#define BPS_GDSC						0
+#define IFE_0_GDSC						1
+#define IFE_1_GDSC						2
+#define IPE_0_GDSC						3
+#define TITAN_TOP_GDSC						4
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR						0
+#define CAM_CC_CAMNOC_BCR					1
+#define CAM_CC_CCI_BCR						2
+#define CAM_CC_CPAS_BCR						3
+#define CAM_CC_CSI0PHY_BCR					4
+#define CAM_CC_CSI1PHY_BCR					5
+#define CAM_CC_CSI2PHY_BCR					6
+#define CAM_CC_ICP_BCR						7
+#define CAM_CC_IFE_0_BCR					8
+#define CAM_CC_IFE_1_BCR					9
+#define CAM_CC_IFE_LITE_BCR					10
+#define CAM_CC_IPE_0_BCR					11
+#define CAM_CC_JPEG_BCR						12
+#define CAM_CC_LRME_BCR						13
+#define CAM_CC_MCLK0_BCR					14
+#define CAM_CC_MCLK1_BCR					15
+#define CAM_CC_MCLK2_BCR					16
+#define CAM_CC_MCLK3_BCR					17
+#define CAM_CC_TITAN_TOP_BCR					18
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,qcs615-dispcc.h b/include/dt-bindings/clock/qcom,qcs615-dispcc.h
new file mode 100644
index 00000000000..9a29945c576
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-dispcc.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_QCS615_H
+
+/* DISP_CC clocks */
+#define DISP_CC_MDSS_AHB_CLK					0
+#define DISP_CC_MDSS_AHB_CLK_SRC				1
+#define DISP_CC_MDSS_BYTE0_CLK					2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				5
+#define DISP_CC_MDSS_DP_AUX_CLK					6
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC				7
+#define DISP_CC_MDSS_DP_CRYPTO_CLK				8
+#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				9
+#define DISP_CC_MDSS_DP_LINK_CLK				10
+#define DISP_CC_MDSS_DP_LINK_CLK_SRC				11
+#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC			12
+#define DISP_CC_MDSS_DP_LINK_INTF_CLK				13
+#define DISP_CC_MDSS_DP_PIXEL1_CLK				14
+#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				15
+#define DISP_CC_MDSS_DP_PIXEL_CLK				16
+#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				17
+#define DISP_CC_MDSS_ESC0_CLK					18
+#define DISP_CC_MDSS_ESC0_CLK_SRC				19
+#define DISP_CC_MDSS_MDP_CLK					20
+#define DISP_CC_MDSS_MDP_CLK_SRC				21
+#define DISP_CC_MDSS_MDP_LUT_CLK				22
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				23
+#define DISP_CC_MDSS_PCLK0_CLK					24
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				25
+#define DISP_CC_MDSS_ROT_CLK					26
+#define DISP_CC_MDSS_ROT_CLK_SRC				27
+#define DISP_CC_MDSS_RSCC_AHB_CLK				28
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK				29
+#define DISP_CC_MDSS_VSYNC_CLK					30
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				31
+#define DISP_CC_PLL0						32
+#define DISP_CC_XO_CLK						33
+
+/* DISP_CC power domains */
+#define MDSS_CORE_GDSC						0
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_RSCC_BCR					1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,qcs615-gpucc.h b/include/dt-bindings/clock/qcom,qcs615-gpucc.h
new file mode 100644
index 00000000000..6d8394b90d5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-gpucc.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
+
+/* GPU_CC clocks */
+#define CRC_DIV_PLL0						0
+#define CRC_DIV_PLL1						1
+#define GPU_CC_PLL0						2
+#define GPU_CC_PLL1						3
+#define GPU_CC_CRC_AHB_CLK					4
+#define GPU_CC_CX_GFX3D_CLK					5
+#define GPU_CC_CX_GFX3D_SLV_CLK					6
+#define GPU_CC_CX_GMU_CLK					7
+#define GPU_CC_CX_SNOC_DVM_CLK					8
+#define GPU_CC_CXO_AON_CLK					9
+#define GPU_CC_CXO_CLK						10
+#define GPU_CC_GMU_CLK_SRC					11
+#define GPU_CC_GX_GFX3D_CLK					12
+#define GPU_CC_GX_GFX3D_CLK_SRC					13
+#define GPU_CC_GX_GMU_CLK					14
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK				15
+#define GPU_CC_SLEEP_CLK					16
+
+/* GPU_CC power domains */
+#define CX_GDSC							0
+#define GX_GDSC							1
+
+/* GPU_CC resets */
+#define GPU_CC_CX_BCR						0
+#define GPU_CC_GFX3D_AON_BCR					1
+#define GPU_CC_GMU_BCR						2
+#define GPU_CC_GX_BCR						3
+#define GPU_CC_XO_BCR						4
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,qcs615-videocc.h b/include/dt-bindings/clock/qcom,qcs615-videocc.h
new file mode 100644
index 00000000000..0ca3efb2110
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,qcs615-videocc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_QCS615_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_SLEEP_CLK					0
+#define VIDEO_CC_SLEEP_CLK_SRC					1
+#define VIDEO_CC_VCODEC0_AXI_CLK				2
+#define VIDEO_CC_VCODEC0_CORE_CLK				3
+#define VIDEO_CC_VENUS_AHB_CLK					4
+#define VIDEO_CC_VENUS_CLK_SRC					5
+#define VIDEO_CC_VENUS_CTL_AXI_CLK				6
+#define VIDEO_CC_VENUS_CTL_CORE_CLK				7
+#define VIDEO_CC_XO_CLK						8
+#define VIDEO_PLL0						9
+
+/* VIDEO_CC power domains */
+#define VCODEC0_GDSC						0
+#define VENUS_GDSC						1
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_VCODEC0_BCR					1
+#define VIDEO_CC_VENUS_BCR					2
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sc8180x-camcc.h b/include/dt-bindings/clock/qcom,sc8180x-camcc.h
new file mode 100644
index 00000000000..3e57b80f65e
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sc8180x-camcc.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK					0
+#define CAM_CC_BPS_AREG_CLK					1
+#define CAM_CC_BPS_AXI_CLK					2
+#define CAM_CC_BPS_CLK						3
+#define CAM_CC_BPS_CLK_SRC					4
+#define CAM_CC_CAMNOC_AXI_CLK					5
+#define CAM_CC_CAMNOC_AXI_CLK_SRC				6
+#define CAM_CC_CAMNOC_DCD_XO_CLK				7
+#define CAM_CC_CCI_0_CLK					8
+#define CAM_CC_CCI_0_CLK_SRC					9
+#define CAM_CC_CCI_1_CLK					10
+#define CAM_CC_CCI_1_CLK_SRC					11
+#define CAM_CC_CCI_2_CLK					12
+#define CAM_CC_CCI_2_CLK_SRC					13
+#define CAM_CC_CCI_3_CLK					14
+#define CAM_CC_CCI_3_CLK_SRC					15
+#define CAM_CC_CORE_AHB_CLK					16
+#define CAM_CC_CPAS_AHB_CLK					17
+#define CAM_CC_CPHY_RX_CLK_SRC					18
+#define CAM_CC_CSI0PHYTIMER_CLK					19
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				20
+#define CAM_CC_CSI1PHYTIMER_CLK					21
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				22
+#define CAM_CC_CSI2PHYTIMER_CLK					23
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				24
+#define CAM_CC_CSI3PHYTIMER_CLK					25
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				26
+#define CAM_CC_CSIPHY0_CLK					27
+#define CAM_CC_CSIPHY1_CLK					28
+#define CAM_CC_CSIPHY2_CLK					29
+#define CAM_CC_CSIPHY3_CLK					30
+#define CAM_CC_FAST_AHB_CLK_SRC					31
+#define CAM_CC_FD_CORE_CLK					32
+#define CAM_CC_FD_CORE_CLK_SRC					33
+#define CAM_CC_FD_CORE_UAR_CLK					34
+#define CAM_CC_ICP_AHB_CLK					35
+#define CAM_CC_ICP_CLK						36
+#define CAM_CC_ICP_CLK_SRC					37
+#define CAM_CC_IFE_0_AXI_CLK					38
+#define CAM_CC_IFE_0_CLK					39
+#define CAM_CC_IFE_0_CLK_SRC					40
+#define CAM_CC_IFE_0_CPHY_RX_CLK				41
+#define CAM_CC_IFE_0_CSID_CLK					42
+#define CAM_CC_IFE_0_CSID_CLK_SRC				43
+#define CAM_CC_IFE_0_DSP_CLK					44
+#define CAM_CC_IFE_1_AXI_CLK					45
+#define CAM_CC_IFE_1_CLK					46
+#define CAM_CC_IFE_1_CLK_SRC					47
+#define CAM_CC_IFE_1_CPHY_RX_CLK				48
+#define CAM_CC_IFE_1_CSID_CLK					49
+#define CAM_CC_IFE_1_CSID_CLK_SRC				50
+#define CAM_CC_IFE_1_DSP_CLK					51
+#define CAM_CC_IFE_2_AXI_CLK					52
+#define CAM_CC_IFE_2_CLK					53
+#define CAM_CC_IFE_2_CLK_SRC					54
+#define CAM_CC_IFE_2_CPHY_RX_CLK				55
+#define CAM_CC_IFE_2_CSID_CLK					56
+#define CAM_CC_IFE_2_CSID_CLK_SRC				57
+#define CAM_CC_IFE_2_DSP_CLK					58
+#define CAM_CC_IFE_3_AXI_CLK					59
+#define CAM_CC_IFE_3_CLK					60
+#define CAM_CC_IFE_3_CLK_SRC					61
+#define CAM_CC_IFE_3_CPHY_RX_CLK				62
+#define CAM_CC_IFE_3_CSID_CLK					63
+#define CAM_CC_IFE_3_CSID_CLK_SRC				64
+#define CAM_CC_IFE_3_DSP_CLK					65
+#define CAM_CC_IFE_LITE_0_CLK					66
+#define CAM_CC_IFE_LITE_0_CLK_SRC				67
+#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK				68
+#define CAM_CC_IFE_LITE_0_CSID_CLK				69
+#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC				70
+#define CAM_CC_IFE_LITE_1_CLK					71
+#define CAM_CC_IFE_LITE_1_CLK_SRC				72
+#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK				73
+#define CAM_CC_IFE_LITE_1_CSID_CLK				74
+#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC				75
+#define CAM_CC_IFE_LITE_2_CLK					76
+#define CAM_CC_IFE_LITE_2_CLK_SRC				77
+#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK				78
+#define CAM_CC_IFE_LITE_2_CSID_CLK				79
+#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC				80
+#define CAM_CC_IFE_LITE_3_CLK					81
+#define CAM_CC_IFE_LITE_3_CLK_SRC				82
+#define CAM_CC_IFE_LITE_3_CPHY_RX_CLK				83
+#define CAM_CC_IFE_LITE_3_CSID_CLK				84
+#define CAM_CC_IFE_LITE_3_CSID_CLK_SRC				85
+#define CAM_CC_IPE_0_AHB_CLK					86
+#define CAM_CC_IPE_0_AREG_CLK					87
+#define CAM_CC_IPE_0_AXI_CLK					88
+#define CAM_CC_IPE_0_CLK					89
+#define CAM_CC_IPE_0_CLK_SRC					90
+#define CAM_CC_IPE_1_AHB_CLK					91
+#define CAM_CC_IPE_1_AREG_CLK					92
+#define CAM_CC_IPE_1_AXI_CLK					93
+#define CAM_CC_IPE_1_CLK					94
+#define CAM_CC_JPEG_CLK						95
+#define CAM_CC_JPEG_CLK_SRC					96
+#define CAM_CC_LRME_CLK						97
+#define CAM_CC_LRME_CLK_SRC					98
+#define CAM_CC_MCLK0_CLK					99
+#define CAM_CC_MCLK0_CLK_SRC					100
+#define CAM_CC_MCLK1_CLK					101
+#define CAM_CC_MCLK1_CLK_SRC					102
+#define CAM_CC_MCLK2_CLK					103
+#define CAM_CC_MCLK2_CLK_SRC					104
+#define CAM_CC_MCLK3_CLK					105
+#define CAM_CC_MCLK3_CLK_SRC					106
+#define CAM_CC_MCLK4_CLK					107
+#define CAM_CC_MCLK4_CLK_SRC					108
+#define CAM_CC_MCLK5_CLK					109
+#define CAM_CC_MCLK5_CLK_SRC					110
+#define CAM_CC_MCLK6_CLK					111
+#define CAM_CC_MCLK6_CLK_SRC					112
+#define CAM_CC_MCLK7_CLK					113
+#define CAM_CC_MCLK7_CLK_SRC					114
+#define CAM_CC_PLL0						115
+#define CAM_CC_PLL0_OUT_EVEN					116
+#define CAM_CC_PLL0_OUT_ODD					117
+#define CAM_CC_PLL1						118
+#define CAM_CC_PLL2						119
+#define CAM_CC_PLL2_OUT_MAIN					120
+#define CAM_CC_PLL3						121
+#define CAM_CC_PLL4						122
+#define CAM_CC_PLL5						123
+#define CAM_CC_PLL6						124
+#define CAM_CC_SLOW_AHB_CLK_SRC					125
+#define CAM_CC_XO_CLK_SRC					126
+
+
+/* CAM_CC power domains */
+#define BPS_GDSC						0
+#define IFE_0_GDSC						1
+#define IFE_1_GDSC						2
+#define IFE_2_GDSC						3
+#define IFE_3_GDSC						4
+#define IPE_0_GDSC						5
+#define IPE_1_GDSC						6
+#define TITAN_TOP_GDSC						7
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR						0
+#define CAM_CC_CAMNOC_BCR					1
+#define CAM_CC_CCI_BCR						2
+#define CAM_CC_CPAS_BCR						3
+#define CAM_CC_CSI0PHY_BCR					4
+#define CAM_CC_CSI1PHY_BCR					5
+#define CAM_CC_CSI2PHY_BCR					6
+#define CAM_CC_CSI3PHY_BCR					7
+#define CAM_CC_FD_BCR						8
+#define CAM_CC_ICP_BCR						9
+#define CAM_CC_IFE_0_BCR					10
+#define CAM_CC_IFE_1_BCR					11
+#define CAM_CC_IFE_2_BCR					12
+#define CAM_CC_IFE_3_BCR					13
+#define CAM_CC_IFE_LITE_0_BCR					14
+#define CAM_CC_IFE_LITE_1_BCR					15
+#define CAM_CC_IFE_LITE_2_BCR					16
+#define CAM_CC_IFE_LITE_3_BCR					17
+#define CAM_CC_IPE_0_BCR					18
+#define CAM_CC_IPE_1_BCR					19
+#define CAM_CC_JPEG_BCR						20
+#define CAM_CC_LRME_BCR						21
+#define CAM_CC_MCLK0_BCR					22
+#define CAM_CC_MCLK1_BCR					23
+#define CAM_CC_MCLK2_BCR					24
+#define CAM_CC_MCLK3_BCR					25
+#define CAM_CC_MCLK4_BCR					26
+#define CAM_CC_MCLK5_BCR					27
+#define CAM_CC_MCLK6_BCR					28
+#define CAM_CC_MCLK7_BCR					29
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 24ba9e2a5cf..710c340f24a 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -482,4 +482,6 @@
 #define GCC_USB_1_PHY_BCR					85
 #define GCC_USB_2_PHY_BCR					86
 #define GCC_VIDEO_BCR						87
+#define GCC_VIDEO_AXI0_CLK_ARES					88
+#define GCC_VIDEO_AXI1_CLK_ARES					89
 #endif
diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 13199334377..e1f65f1928c 100644
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -200,57 +200,4 @@
 #define R9A07G043_AX45MP_CORE0_RESETN	78	/* RZ/Five Only */
 #define R9A07G043_IAX45_RESETN		79	/* RZ/Five Only */
 
-/* Power domain IDs. */
-#define R9A07G043_PD_ALWAYS_ON		0
-#define R9A07G043_PD_GIC		1	/* RZ/G2UL Only */
-#define R9A07G043_PD_IA55		2	/* RZ/G2UL Only */
-#define R9A07G043_PD_MHU		3	/* RZ/G2UL Only */
-#define R9A07G043_PD_CORESIGHT		4	/* RZ/G2UL Only */
-#define R9A07G043_PD_SYC		5	/* RZ/G2UL Only */
-#define R9A07G043_PD_DMAC		6
-#define R9A07G043_PD_GTM0		7
-#define R9A07G043_PD_GTM1		8
-#define R9A07G043_PD_GTM2		9
-#define R9A07G043_PD_MTU		10
-#define R9A07G043_PD_POE3		11
-#define R9A07G043_PD_WDT0		12
-#define R9A07G043_PD_SPI		13
-#define R9A07G043_PD_SDHI0		14
-#define R9A07G043_PD_SDHI1		15
-#define R9A07G043_PD_ISU		16	/* RZ/G2UL Only */
-#define R9A07G043_PD_CRU		17	/* RZ/G2UL Only */
-#define R9A07G043_PD_LCDC		18	/* RZ/G2UL Only */
-#define R9A07G043_PD_SSI0		19
-#define R9A07G043_PD_SSI1		20
-#define R9A07G043_PD_SSI2		21
-#define R9A07G043_PD_SSI3		22
-#define R9A07G043_PD_SRC		23
-#define R9A07G043_PD_USB0		24
-#define R9A07G043_PD_USB1		25
-#define R9A07G043_PD_USB_PHY		26
-#define R9A07G043_PD_ETHER0		27
-#define R9A07G043_PD_ETHER1		28
-#define R9A07G043_PD_I2C0		29
-#define R9A07G043_PD_I2C1		30
-#define R9A07G043_PD_I2C2		31
-#define R9A07G043_PD_I2C3		32
-#define R9A07G043_PD_SCIF0		33
-#define R9A07G043_PD_SCIF1		34
-#define R9A07G043_PD_SCIF2		35
-#define R9A07G043_PD_SCIF3		36
-#define R9A07G043_PD_SCIF4		37
-#define R9A07G043_PD_SCI0		38
-#define R9A07G043_PD_SCI1		39
-#define R9A07G043_PD_IRDA		40
-#define R9A07G043_PD_RSPI0		41
-#define R9A07G043_PD_RSPI1		42
-#define R9A07G043_PD_RSPI2		43
-#define R9A07G043_PD_CANFD		44
-#define R9A07G043_PD_ADC		45
-#define R9A07G043_PD_TSU		46
-#define R9A07G043_PD_PLIC		47	/* RZ/Five Only */
-#define R9A07G043_PD_IAX45		48	/* RZ/Five Only */
-#define R9A07G043_PD_NCEPLDM		49	/* RZ/Five Only */
-#define R9A07G043_PD_NCEPLMT		50	/* RZ/Five Only */
-
 #endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index e209f96f92b..0bb17ff1a01 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -217,62 +217,4 @@
 #define R9A07G044_ADC_ADRST_N		82
 #define R9A07G044_TSU_PRESETN		83
 
-/* Power domain IDs. */
-#define R9A07G044_PD_ALWAYS_ON		0
-#define R9A07G044_PD_GIC		1
-#define R9A07G044_PD_IA55		2
-#define R9A07G044_PD_MHU		3
-#define R9A07G044_PD_CORESIGHT		4
-#define R9A07G044_PD_SYC		5
-#define R9A07G044_PD_DMAC		6
-#define R9A07G044_PD_GTM0		7
-#define R9A07G044_PD_GTM1		8
-#define R9A07G044_PD_GTM2		9
-#define R9A07G044_PD_MTU		10
-#define R9A07G044_PD_POE3		11
-#define R9A07G044_PD_GPT		12
-#define R9A07G044_PD_POEGA		13
-#define R9A07G044_PD_POEGB		14
-#define R9A07G044_PD_POEGC		15
-#define R9A07G044_PD_POEGD		16
-#define R9A07G044_PD_WDT0		17
-#define R9A07G044_PD_WDT1		18
-#define R9A07G044_PD_SPI		19
-#define R9A07G044_PD_SDHI0		20
-#define R9A07G044_PD_SDHI1		21
-#define R9A07G044_PD_3DGE		22
-#define R9A07G044_PD_ISU		23
-#define R9A07G044_PD_VCPL4		24
-#define R9A07G044_PD_CRU		25
-#define R9A07G044_PD_MIPI_DSI		26
-#define R9A07G044_PD_LCDC		27
-#define R9A07G044_PD_SSI0		28
-#define R9A07G044_PD_SSI1		29
-#define R9A07G044_PD_SSI2		30
-#define R9A07G044_PD_SSI3		31
-#define R9A07G044_PD_SRC		32
-#define R9A07G044_PD_USB0		33
-#define R9A07G044_PD_USB1		34
-#define R9A07G044_PD_USB_PHY		35
-#define R9A07G044_PD_ETHER0		36
-#define R9A07G044_PD_ETHER1		37
-#define R9A07G044_PD_I2C0		38
-#define R9A07G044_PD_I2C1		39
-#define R9A07G044_PD_I2C2		40
-#define R9A07G044_PD_I2C3		41
-#define R9A07G044_PD_SCIF0		42
-#define R9A07G044_PD_SCIF1		43
-#define R9A07G044_PD_SCIF2		44
-#define R9A07G044_PD_SCIF3		45
-#define R9A07G044_PD_SCIF4		46
-#define R9A07G044_PD_SCI0		47
-#define R9A07G044_PD_SCI1		48
-#define R9A07G044_PD_IRDA		49
-#define R9A07G044_PD_RSPI0		50
-#define R9A07G044_PD_RSPI1		51
-#define R9A07G044_PD_RSPI2		52
-#define R9A07G044_PD_CANFD		53
-#define R9A07G044_PD_ADC		54
-#define R9A07G044_PD_TSU		55
-
 #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
diff --git a/include/dt-bindings/clock/r9a07g054-cpg.h b/include/dt-bindings/clock/r9a07g054-cpg.h
index 2c99f89397c..43f4dbda872 100644
--- a/include/dt-bindings/clock/r9a07g054-cpg.h
+++ b/include/dt-bindings/clock/r9a07g054-cpg.h
@@ -226,62 +226,4 @@
 #define R9A07G054_TSU_PRESETN		83
 #define R9A07G054_STPAI_ARESETN		84
 
-/* Power domain IDs. */
-#define R9A07G054_PD_ALWAYS_ON		0
-#define R9A07G054_PD_GIC		1
-#define R9A07G054_PD_IA55		2
-#define R9A07G054_PD_MHU		3
-#define R9A07G054_PD_CORESIGHT		4
-#define R9A07G054_PD_SYC		5
-#define R9A07G054_PD_DMAC		6
-#define R9A07G054_PD_GTM0		7
-#define R9A07G054_PD_GTM1		8
-#define R9A07G054_PD_GTM2		9
-#define R9A07G054_PD_MTU		10
-#define R9A07G054_PD_POE3		11
-#define R9A07G054_PD_GPT		12
-#define R9A07G054_PD_POEGA		13
-#define R9A07G054_PD_POEGB		14
-#define R9A07G054_PD_POEGC		15
-#define R9A07G054_PD_POEGD		16
-#define R9A07G054_PD_WDT0		17
-#define R9A07G054_PD_WDT1		18
-#define R9A07G054_PD_SPI		19
-#define R9A07G054_PD_SDHI0		20
-#define R9A07G054_PD_SDHI1		21
-#define R9A07G054_PD_3DGE		22
-#define R9A07G054_PD_ISU		23
-#define R9A07G054_PD_VCPL4		24
-#define R9A07G054_PD_CRU		25
-#define R9A07G054_PD_MIPI_DSI		26
-#define R9A07G054_PD_LCDC		27
-#define R9A07G054_PD_SSI0		28
-#define R9A07G054_PD_SSI1		29
-#define R9A07G054_PD_SSI2		30
-#define R9A07G054_PD_SSI3		31
-#define R9A07G054_PD_SRC		32
-#define R9A07G054_PD_USB0		33
-#define R9A07G054_PD_USB1		34
-#define R9A07G054_PD_USB_PHY		35
-#define R9A07G054_PD_ETHER0		36
-#define R9A07G054_PD_ETHER1		37
-#define R9A07G054_PD_I2C0		38
-#define R9A07G054_PD_I2C1		39
-#define R9A07G054_PD_I2C2		40
-#define R9A07G054_PD_I2C3		41
-#define R9A07G054_PD_SCIF0		42
-#define R9A07G054_PD_SCIF1		43
-#define R9A07G054_PD_SCIF2		44
-#define R9A07G054_PD_SCIF3		45
-#define R9A07G054_PD_SCIF4		46
-#define R9A07G054_PD_SCI0		47
-#define R9A07G054_PD_SCI1		48
-#define R9A07G054_PD_IRDA		49
-#define R9A07G054_PD_RSPI0		50
-#define R9A07G054_PD_RSPI1		51
-#define R9A07G054_PD_RSPI2		52
-#define R9A07G054_PD_CANFD		53
-#define R9A07G054_PD_ADC		54
-#define R9A07G054_PD_TSU		55
-
 #endif /* __DT_BINDINGS_CLOCK_R9A07G054_CPG_H__ */
diff --git a/include/dt-bindings/clock/r9a08g045-cpg.h b/include/dt-bindings/clock/r9a08g045-cpg.h
index 311521fe4b5..410725b778a 100644
--- a/include/dt-bindings/clock/r9a08g045-cpg.h
+++ b/include/dt-bindings/clock/r9a08g045-cpg.h
@@ -239,75 +239,4 @@
 #define R9A08G045_I3C_PRESETN		92
 #define R9A08G045_VBAT_BRESETN		93
 
-/* Power domain IDs. */
-#define R9A08G045_PD_ALWAYS_ON		0
-#define R9A08G045_PD_GIC		1
-#define R9A08G045_PD_IA55		2
-#define R9A08G045_PD_MHU		3
-#define R9A08G045_PD_CORESIGHT		4
-#define R9A08G045_PD_SYC		5
-#define R9A08G045_PD_DMAC		6
-#define R9A08G045_PD_GTM0		7
-#define R9A08G045_PD_GTM1		8
-#define R9A08G045_PD_GTM2		9
-#define R9A08G045_PD_GTM3		10
-#define R9A08G045_PD_GTM4		11
-#define R9A08G045_PD_GTM5		12
-#define R9A08G045_PD_GTM6		13
-#define R9A08G045_PD_GTM7		14
-#define R9A08G045_PD_MTU		15
-#define R9A08G045_PD_POE3		16
-#define R9A08G045_PD_GPT		17
-#define R9A08G045_PD_POEGA		18
-#define R9A08G045_PD_POEGB		19
-#define R9A08G045_PD_POEGC		20
-#define R9A08G045_PD_POEGD		21
-#define R9A08G045_PD_WDT0		22
-#define R9A08G045_PD_XSPI		23
-#define R9A08G045_PD_SDHI0		24
-#define R9A08G045_PD_SDHI1		25
-#define R9A08G045_PD_SDHI2		26
-#define R9A08G045_PD_SSI0		27
-#define R9A08G045_PD_SSI1		28
-#define R9A08G045_PD_SSI2		29
-#define R9A08G045_PD_SSI3		30
-#define R9A08G045_PD_SRC		31
-#define R9A08G045_PD_USB0		32
-#define R9A08G045_PD_USB1		33
-#define R9A08G045_PD_USB_PHY		34
-#define R9A08G045_PD_ETHER0		35
-#define R9A08G045_PD_ETHER1		36
-#define R9A08G045_PD_I2C0		37
-#define R9A08G045_PD_I2C1		38
-#define R9A08G045_PD_I2C2		39
-#define R9A08G045_PD_I2C3		40
-#define R9A08G045_PD_SCIF0		41
-#define R9A08G045_PD_SCIF1		42
-#define R9A08G045_PD_SCIF2		43
-#define R9A08G045_PD_SCIF3		44
-#define R9A08G045_PD_SCIF4		45
-#define R9A08G045_PD_SCIF5		46
-#define R9A08G045_PD_SCI0		47
-#define R9A08G045_PD_SCI1		48
-#define R9A08G045_PD_IRDA		49
-#define R9A08G045_PD_RSPI0		50
-#define R9A08G045_PD_RSPI1		51
-#define R9A08G045_PD_RSPI2		52
-#define R9A08G045_PD_RSPI3		53
-#define R9A08G045_PD_RSPI4		54
-#define R9A08G045_PD_CANFD		55
-#define R9A08G045_PD_ADC		56
-#define R9A08G045_PD_TSU		57
-#define R9A08G045_PD_OCTA		58
-#define R9A08G045_PD_PDM		59
-#define R9A08G045_PD_PCI		60
-#define R9A08G045_PD_SPDIF		61
-#define R9A08G045_PD_I3C		62
-#define R9A08G045_PD_VBAT		63
-
-#define R9A08G045_PD_DDR		64
-#define R9A08G045_PD_TZCDDR		65
-#define R9A08G045_PD_OTFDE_DDR		66
-#define R9A08G045_PD_RTC		67
-
 #endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */
diff --git a/include/dt-bindings/clock/raspberrypi,rp1-clocks.h b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
new file mode 100644
index 00000000000..248efb895f3
--- /dev/null
+++ b/include/dt-bindings/clock/raspberrypi,rp1-clocks.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2021 Raspberry Pi Ltd.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
+#define __DT_BINDINGS_CLOCK_RASPBERRYPI_RP1
+
+#define RP1_PLL_SYS_CORE		0
+#define RP1_PLL_AUDIO_CORE		1
+#define RP1_PLL_VIDEO_CORE		2
+
+#define RP1_PLL_SYS			3
+#define RP1_PLL_AUDIO			4
+#define RP1_PLL_VIDEO			5
+
+#define RP1_PLL_SYS_PRI_PH		6
+#define RP1_PLL_SYS_SEC_PH		7
+#define RP1_PLL_AUDIO_PRI_PH		8
+
+#define RP1_PLL_SYS_SEC			9
+#define RP1_PLL_AUDIO_SEC		10
+#define RP1_PLL_VIDEO_SEC		11
+
+#define RP1_CLK_SYS			12
+#define RP1_CLK_SLOW_SYS		13
+#define RP1_CLK_DMA			14
+#define RP1_CLK_UART			15
+#define RP1_CLK_ETH			16
+#define RP1_CLK_PWM0			17
+#define RP1_CLK_PWM1			18
+#define RP1_CLK_AUDIO_IN		19
+#define RP1_CLK_AUDIO_OUT		20
+#define RP1_CLK_I2S			21
+#define RP1_CLK_MIPI0_CFG		22
+#define RP1_CLK_MIPI1_CFG		23
+#define RP1_CLK_PCIE_AUX		24
+#define RP1_CLK_USBH0_MICROFRAME	25
+#define RP1_CLK_USBH1_MICROFRAME	26
+#define RP1_CLK_USBH0_SUSPEND		27
+#define RP1_CLK_USBH1_SUSPEND		28
+#define RP1_CLK_ETH_TSU			29
+#define RP1_CLK_ADC			30
+#define RP1_CLK_SDIO_TIMER		31
+#define RP1_CLK_SDIO_ALT_SRC		32
+#define RP1_CLK_GP0			33
+#define RP1_CLK_GP1			34
+#define RP1_CLK_GP2			35
+#define RP1_CLK_GP3			36
+#define RP1_CLK_GP4			37
+#define RP1_CLK_GP5			38
+#define RP1_CLK_VEC			39
+#define RP1_CLK_DPI			40
+#define RP1_CLK_MIPI0_DPI		41
+#define RP1_CLK_MIPI1_DPI		42
+
+/* Extra PLL output channels - RP1B0 only */
+#define RP1_PLL_VIDEO_PRI_PH		43
+#define RP1_PLL_AUDIO_TERN		44
+
+#endif
diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
index f4905b27f8d..a9af5af9e3a 100644
--- a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
@@ -20,5 +20,6 @@
 #define R9A09G056_USB2_0_CLK_CORE0		9
 #define R9A09G056_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G056_GBETH_1_CLK_PTP_REF_I		11
+#define R9A09G056_SPI_CLK_SPI			12
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
index 884dbeb1e13..5346a898ab6 100644
--- a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h
@@ -21,5 +21,6 @@
 #define R9A09G057_USB2_0_CLK_CORE1		10
 #define R9A09G057_GBETH_0_CLK_PTP_REF_I		11
 #define R9A09G057_GBETH_1_CLK_PTP_REF_I		12
+#define R9A09G057_SPI_CLK_SPI			13
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
new file mode 100644
index 00000000000..7ecc4f0b235
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G077 CPG Core Clocks */
+#define R9A09G077_CLK_CA55C0		0
+#define R9A09G077_CLK_CA55C1		1
+#define R9A09G077_CLK_CA55C2		2
+#define R9A09G077_CLK_CA55C3		3
+#define R9A09G077_CLK_CA55S		4
+#define R9A09G077_CLK_CR52_CPU0		5
+#define R9A09G077_CLK_CR52_CPU1		6
+#define R9A09G077_CLK_CKIO		7
+#define R9A09G077_CLK_PCLKAH		8
+#define R9A09G077_CLK_PCLKAM		9
+#define R9A09G077_CLK_PCLKAL		10
+#define R9A09G077_CLK_PCLKGPTL		11
+#define R9A09G077_CLK_PCLKH		12
+#define R9A09G077_CLK_PCLKM		13
+#define R9A09G077_CLK_PCLKL		14
+#define R9A09G077_SDHI_CLKHS		15
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
new file mode 100644
index 00000000000..925e5770392
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A09G087 CPG Core Clocks */
+#define R9A09G087_CLK_CA55C0		0
+#define R9A09G087_CLK_CA55C1		1
+#define R9A09G087_CLK_CA55C2		2
+#define R9A09G087_CLK_CA55C3		3
+#define R9A09G087_CLK_CA55S		4
+#define R9A09G087_CLK_CR52_CPU0		5
+#define R9A09G087_CLK_CR52_CPU1		6
+#define R9A09G087_CLK_CKIO		7
+#define R9A09G087_CLK_PCLKAH		8
+#define R9A09G087_CLK_PCLKAM		9
+#define R9A09G087_CLK_PCLKAL		10
+#define R9A09G087_CLK_PCLKGPTL		11
+#define R9A09G087_CLK_PCLKH		12
+#define R9A09G087_CLK_PCLKM		13
+#define R9A09G087_CLK_PCLKL		14
+#define R9A09G087_SDHI_CLKHS		15
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 5e6896e9627..93e6233d135 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -286,4 +286,13 @@
 #define CLK_MOUT_HSI1_USBDRD_USER	3
 #define CLK_MOUT_HSI1_USBDRD		4
 
+/* CMU_HSI2 */
+#define FOUT_PLL_ETH                    1
+#define CLK_MOUT_HSI2_NOC_UFS_USER      2
+#define CLK_MOUT_HSI2_UFS_EMBD_USER     3
+#define CLK_MOUT_HSI2_ETHERNET          4
+#define CLK_MOUT_HSI2_ETHERNET_USER     5
+#define CLK_DOUT_HSI2_ETHERNET          6
+#define CLK_DOUT_HSI2_ETHERNET_PTP      7
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h
index 35968ae9824..2714c3fe66c 100644
--- a/include/dt-bindings/clock/spacemit,k1-syscon.h
+++ b/include/dt-bindings/clock/spacemit,k1-syscon.h
@@ -78,6 +78,9 @@
 #define CLK_APB			31
 #define CLK_WDT_BUS		32
 
+/* MPMU resets */
+#define RESET_WDT		0
+
 /* APBC clocks */
 #define CLK_UART0		0
 #define CLK_UART2		1
@@ -180,6 +183,59 @@
 #define CLK_TSEN_BUS		98
 #define CLK_IPC_AP2AUD_BUS	99
 
+/* APBC resets */
+#define RESET_UART0		0
+#define RESET_UART2		1
+#define RESET_UART3		2
+#define RESET_UART4		3
+#define RESET_UART5		4
+#define RESET_UART6		5
+#define RESET_UART7		6
+#define RESET_UART8		7
+#define RESET_UART9		8
+#define RESET_GPIO		9
+#define RESET_PWM0		10
+#define RESET_PWM1		11
+#define RESET_PWM2		12
+#define RESET_PWM3		13
+#define RESET_PWM4		14
+#define RESET_PWM5		15
+#define RESET_PWM6		16
+#define RESET_PWM7		17
+#define RESET_PWM8		18
+#define RESET_PWM9		19
+#define RESET_PWM10		20
+#define RESET_PWM11		21
+#define RESET_PWM12		22
+#define RESET_PWM13		23
+#define RESET_PWM14		24
+#define RESET_PWM15		25
+#define RESET_PWM16		26
+#define RESET_PWM17		27
+#define RESET_PWM18		28
+#define RESET_PWM19		29
+#define RESET_SSP3		30
+#define RESET_RTC		31
+#define RESET_TWSI0		32
+#define RESET_TWSI1		33
+#define RESET_TWSI2		34
+#define RESET_TWSI4		35
+#define RESET_TWSI5		36
+#define RESET_TWSI6		37
+#define RESET_TWSI7		38
+#define RESET_TWSI8		39
+#define RESET_TIMERS1		40
+#define RESET_TIMERS2		41
+#define RESET_AIB		42
+#define RESET_ONEWIRE		43
+#define RESET_SSPA0		44
+#define RESET_SSPA1		45
+#define RESET_DRO		46
+#define RESET_IR		47
+#define RESET_TSEN		48
+#define RESET_IPC_AP2AUD	49
+#define RESET_CAN0		50
+
 /* APMU clocks */
 #define CLK_CCI550		0
 #define CLK_CPU_C0_HI		1
@@ -244,4 +300,89 @@
 #define CLK_V2D			60
 #define CLK_EMMC_BUS		61
 
+/* APMU resets */
+#define RESET_CCIC_4X		0
+#define RESET_CCIC1_PHY		1
+#define RESET_SDH_AXI		2
+#define RESET_SDH0		3
+#define RESET_SDH1		4
+#define RESET_SDH2		5
+#define RESET_USBP1_AXI		6
+#define RESET_USB_AXI		7
+#define RESET_USB30_AHB		8
+#define RESET_USB30_VCC		9
+#define RESET_USB30_PHY		10
+#define RESET_QSPI		11
+#define RESET_QSPI_BUS		12
+#define RESET_DMA		13
+#define RESET_AES		14
+#define RESET_VPU		15
+#define RESET_GPU		16
+#define RESET_EMMC		17
+#define RESET_EMMC_X		18
+#define RESET_AUDIO_SYS		19
+#define RESET_AUDIO_MCU		20
+#define RESET_AUDIO_APMU	21
+#define RESET_HDMI		22
+#define RESET_PCIE0_MASTER	23
+#define RESET_PCIE0_SLAVE	24
+#define RESET_PCIE0_DBI		25
+#define RESET_PCIE0_GLOBAL	26
+#define RESET_PCIE1_MASTER	27
+#define RESET_PCIE1_SLAVE	28
+#define RESET_PCIE1_DBI		29
+#define RESET_PCIE1_GLOBAL	30
+#define RESET_PCIE2_MASTER	31
+#define RESET_PCIE2_SLAVE	32
+#define RESET_PCIE2_DBI		33
+#define RESET_PCIE2_GLOBAL	34
+#define RESET_EMAC0		35
+#define RESET_EMAC1		36
+#define RESET_JPG		37
+#define RESET_CCIC2PHY		38
+#define RESET_CCIC3PHY		39
+#define RESET_CSI		40
+#define RESET_ISP_CPP		41
+#define RESET_ISP_BUS		42
+#define RESET_ISP		43
+#define RESET_ISP_CI		44
+#define RESET_DPU_MCLK		45
+#define RESET_DPU_ESC		46
+#define RESET_DPU_HCLK		47
+#define RESET_DPU_SPIBUS	48
+#define RESET_DPU_SPI_HBUS	49
+#define RESET_V2D		50
+#define RESET_MIPI		51
+#define RESET_MC		52
+
+/*	RCPU resets	*/
+#define RESET_RCPU_SSP0		0
+#define RESET_RCPU_I2C0		1
+#define RESET_RCPU_UART1	2
+#define RESET_RCPU_IR		3
+#define RESET_RCPU_CAN		4
+#define RESET_RCPU_UART0	5
+#define RESET_RCPU_HDMI_AUDIO	6
+
+/*	RCPU2 resets	*/
+#define RESET_RCPU2_PWM0	0
+#define RESET_RCPU2_PWM1	1
+#define RESET_RCPU2_PWM2	2
+#define RESET_RCPU2_PWM3	3
+#define RESET_RCPU2_PWM4	4
+#define RESET_RCPU2_PWM5	5
+#define RESET_RCPU2_PWM6	6
+#define RESET_RCPU2_PWM7	7
+#define RESET_RCPU2_PWM8	8
+#define RESET_RCPU2_PWM9	9
+
+/*	APBC2 resets	*/
+#define RESET_APBC2_UART1	0
+#define RESET_APBC2_SSP2	1
+#define RESET_APBC2_TWSI3	2
+#define RESET_APBC2_RTC		3
+#define RESET_APBC2_TIMERS0	4
+#define RESET_APBC2_KPC		5
+#define RESET_APBC2_GPIO	6
+
 #endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */
diff --git a/include/dt-bindings/iio/adc/adi,ad7768-1.h b/include/dt-bindings/iio/adc/adi,ad7768-1.h
new file mode 100644
index 00000000000..34d92856a50
--- /dev/null
+++ b/include/dt-bindings/iio/adc/adi,ad7768-1.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_ADI_AD7768_1_H
+#define _DT_BINDINGS_ADI_AD7768_1_H
+
+#define AD7768_TRIGGER_SOURCE_SYNC_OUT  0
+#define AD7768_TRIGGER_SOURCE_GPIO3     1
+#define AD7768_TRIGGER_SOURCE_DRDY      2
+
+#endif /* _DT_BINDINGS_ADI_AD7768_1_H */
diff --git a/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h b/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h
new file mode 100644
index 00000000000..92d135477d0
--- /dev/null
+++ b/include/dt-bindings/iio/adc/mediatek,mt6363-auxadc.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6363_AUXADC_H
+
+/* ADC Channel Index */
+#define MT6363_AUXADC_BATADC		0
+#define MT6363_AUXADC_VCDT		1
+#define MT6363_AUXADC_BAT_TEMP		2
+#define MT6363_AUXADC_CHIP_TEMP		3
+#define MT6363_AUXADC_VSYSSNS		4
+#define MT6363_AUXADC_VTREF		5
+#define MT6363_AUXADC_VCORE_TEMP	6
+#define MT6363_AUXADC_VPROC_TEMP	7
+#define MT6363_AUXADC_VGPU_TEMP		8
+#define MT6363_AUXADC_VIN1		9
+#define MT6363_AUXADC_VIN2		10
+#define MT6363_AUXADC_VIN3		11
+#define MT6363_AUXADC_VIN4		12
+#define MT6363_AUXADC_VIN5		13
+#define MT6363_AUXADC_VIN6		14
+#define MT6363_AUXADC_VIN7		15
+
+#endif
diff --git a/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h b/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h
new file mode 100644
index 00000000000..17cab86d355
--- /dev/null
+++ b/include/dt-bindings/iio/adc/mediatek,mt6373-auxadc.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+
+#ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
+#define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
+
+/* ADC Channel Index */
+#define MT6373_AUXADC_CHIP_TEMP		0
+#define MT6373_AUXADC_VCORE_TEMP	1
+#define MT6373_AUXADC_VPROC_TEMP	2
+#define MT6373_AUXADC_VGPU_TEMP		3
+#define MT6373_AUXADC_VIN1		4
+#define MT6373_AUXADC_VIN2		5
+#define MT6373_AUXADC_VIN3		6
+#define MT6373_AUXADC_VIN4		7
+#define MT6373_AUXADC_VIN5		8
+#define MT6373_AUXADC_VIN6		9
+#define MT6373_AUXADC_VIN7		10
+
+#endif
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index 3b2524e4b66..ca5851e97fa 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -601,6 +601,11 @@
 #define BTN_DPAD_LEFT		0x222
 #define BTN_DPAD_RIGHT		0x223
 
+#define BTN_GRIPL		0x224
+#define BTN_GRIPR		0x225
+#define BTN_GRIPL2		0x226
+#define BTN_GRIPR2		0x227
+
 #define KEY_ALS_TOGGLE		0x230	/* Ambient light sensor */
 #define KEY_ROTATE_LOCK_TOGGLE	0x231	/* Display rotation lock */
 #define KEY_REFRESH_RATE_TOGGLE	0x232	/* Display refresh rate toggle */
@@ -765,6 +770,9 @@
 #define KEY_KBD_LCD_MENU4		0x2bb
 #define KEY_KBD_LCD_MENU5		0x2bc
 
+/* Performance Boost key (Alienware)/G-Mode key (Dell) */
+#define KEY_PERFORMANCE			0x2bd
+
 #define BTN_TRIGGER_HAPPY		0x2c0
 #define BTN_TRIGGER_HAPPY1		0x2c0
 #define BTN_TRIGGER_HAPPY2		0x2c1
diff --git a/include/dt-bindings/interconnect/qcom,milos-rpmh.h b/include/dt-bindings/interconnect/qcom,milos-rpmh.h
new file mode 100644
index 00000000000..9326d7d9c2a
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,milos-rpmh.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
+
+#define MASTER_QUP_1				0
+#define MASTER_UFS_MEM				1
+#define MASTER_USB3_0				2
+#define SLAVE_A1NOC_SNOC			3
+
+#define MASTER_QDSS_BAM				0
+#define MASTER_QSPI_0				1
+#define MASTER_QUP_0				2
+#define MASTER_CRYPTO				3
+#define MASTER_IPA				4
+#define MASTER_QDSS_ETR				5
+#define MASTER_QDSS_ETR_1			6
+#define MASTER_SDCC_1				7
+#define MASTER_SDCC_2				8
+#define SLAVE_A2NOC_SNOC			9
+
+#define MASTER_QUP_CORE_0			0
+#define MASTER_QUP_CORE_1			1
+#define SLAVE_QUP_CORE_0			2
+#define SLAVE_QUP_CORE_1			3
+
+#define MASTER_CNOC_CFG				0
+#define SLAVE_AHB2PHY_SOUTH			1
+#define SLAVE_AHB2PHY_NORTH			2
+#define SLAVE_CAMERA_CFG			3
+#define SLAVE_CLK_CTL				4
+#define SLAVE_RBCPR_CX_CFG			5
+#define SLAVE_RBCPR_MXA_CFG			6
+#define SLAVE_CRYPTO_0_CFG			7
+#define SLAVE_CX_RDPM				8
+#define SLAVE_GFX3D_CFG				9
+#define SLAVE_IMEM_CFG				10
+#define SLAVE_CNOC_MSS				11
+#define SLAVE_MX_2_RDPM				12
+#define SLAVE_MX_RDPM				13
+#define SLAVE_PDM				14
+#define SLAVE_QDSS_CFG				15
+#define SLAVE_QSPI_0				16
+#define SLAVE_QUP_0				17
+#define SLAVE_QUP_1				18
+#define SLAVE_SDC1				19
+#define SLAVE_SDCC_2				20
+#define SLAVE_TCSR				21
+#define SLAVE_TLMM				22
+#define SLAVE_UFS_MEM_CFG			23
+#define SLAVE_USB3_0				24
+#define SLAVE_VENUS_CFG				25
+#define SLAVE_VSENSE_CTRL_CFG			26
+#define SLAVE_WLAN				27
+#define SLAVE_CNOC_MNOC_HF_CFG			28
+#define SLAVE_CNOC_MNOC_SF_CFG			29
+#define SLAVE_NSP_QTB_CFG			30
+#define SLAVE_PCIE_ANOC_CFG			31
+#define SLAVE_WLAN_Q6_THROTTLE_CFG		32
+#define SLAVE_SERVICE_CNOC_CFG			33
+#define SLAVE_QDSS_STM				34
+#define SLAVE_TCU				35
+
+#define MASTER_GEM_NOC_CNOC			0
+#define MASTER_GEM_NOC_PCIE_SNOC		1
+#define SLAVE_AOSS				2
+#define SLAVE_DISPLAY_CFG			3
+#define SLAVE_IPA_CFG				4
+#define SLAVE_IPC_ROUTER_CFG			5
+#define SLAVE_PCIE_0_CFG			6
+#define SLAVE_PCIE_1_CFG			7
+#define SLAVE_PRNG				8
+#define SLAVE_TME_CFG				9
+#define SLAVE_APPSS				10
+#define SLAVE_CNOC_CFG				11
+#define SLAVE_DDRSS_CFG				12
+#define SLAVE_IMEM				13
+#define SLAVE_PIMEM				14
+#define SLAVE_SERVICE_CNOC			15
+#define SLAVE_PCIE_0				16
+#define SLAVE_PCIE_1				17
+
+#define MASTER_GPU_TCU				0
+#define MASTER_SYS_TCU				1
+#define MASTER_APPSS_PROC			2
+#define MASTER_GFX3D				3
+#define MASTER_LPASS_GEM_NOC			4
+#define MASTER_MSS_PROC				5
+#define MASTER_MNOC_HF_MEM_NOC			6
+#define MASTER_MNOC_SF_MEM_NOC			7
+#define MASTER_COMPUTE_NOC			8
+#define MASTER_ANOC_PCIE_GEM_NOC		9
+#define MASTER_SNOC_GC_MEM_NOC			10
+#define MASTER_SNOC_SF_MEM_NOC			11
+#define MASTER_WLAN_Q6				12
+#define SLAVE_GEM_NOC_CNOC			13
+#define SLAVE_LLCC				14
+#define SLAVE_MEM_NOC_PCIE_SNOC			15
+
+#define MASTER_LPASS_PROC			0
+#define SLAVE_LPASS_GEM_NOC			1
+
+#define MASTER_LLCC				0
+#define SLAVE_EBI1				1
+
+#define MASTER_CAMNOC_HF			0
+#define MASTER_CAMNOC_ICP			1
+#define MASTER_CAMNOC_SF			2
+#define MASTER_MDP				3
+#define MASTER_VIDEO				4
+#define MASTER_CNOC_MNOC_HF_CFG			5
+#define MASTER_CNOC_MNOC_SF_CFG			6
+#define SLAVE_MNOC_HF_MEM_NOC			7
+#define SLAVE_MNOC_SF_MEM_NOC			8
+#define SLAVE_SERVICE_MNOC_HF			9
+#define SLAVE_SERVICE_MNOC_SF			10
+
+#define MASTER_CDSP_PROC			0
+#define SLAVE_CDSP_MEM_NOC			1
+
+#define MASTER_PCIE_ANOC_CFG			0
+#define MASTER_PCIE_0				1
+#define MASTER_PCIE_1				2
+#define SLAVE_ANOC_PCIE_GEM_NOC			3
+#define SLAVE_SERVICE_PCIE_ANOC			4
+
+#define MASTER_A1NOC_SNOC			0
+#define MASTER_A2NOC_SNOC			1
+#define MASTER_APSS_NOC				2
+#define MASTER_CNOC_SNOC			3
+#define MASTER_PIMEM				4
+#define MASTER_GIC				5
+#define SLAVE_SNOC_GEM_NOC_GC			6
+#define SLAVE_SNOC_GEM_NOC_SF			7
+
+
+#endif
diff --git a/include/dt-bindings/memory/nvidia,tegra264.h b/include/dt-bindings/memory/nvidia,tegra264.h
new file mode 100644
index 00000000000..521405c01f8
--- /dev/null
+++ b/include/dt-bindings/memory/nvidia,tegra264.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
+#define DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H
+
+#define TEGRA264_SID(x) ((x) << 8)
+
+/*
+ * SMMU stream IDs
+ */
+
+#define TEGRA264_SID_AON       TEGRA264_SID(0x01)
+#define TEGRA264_SID_APE       TEGRA264_SID(0x02)
+#define TEGRA264_SID_ETR       TEGRA264_SID(0x03)
+#define TEGRA264_SID_BPMP      TEGRA264_SID(0x04)
+#define TEGRA264_SID_DCE       TEGRA264_SID(0x05)
+#define TEGRA264_SID_EQOS      TEGRA264_SID(0x06)
+#define TEGRA264_SID_GPCDMA    TEGRA264_SID(0x08)
+#define TEGRA264_SID_DISP      TEGRA264_SID(0x09)
+#define TEGRA264_SID_HDA       TEGRA264_SID(0x0a)
+#define TEGRA264_SID_HOST1X    TEGRA264_SID(0x0b)
+#define TEGRA264_SID_ISP0      TEGRA264_SID(0x0c)
+#define TEGRA264_SID_ISP1      TEGRA264_SID(0x0d)
+#define TEGRA264_SID_PMA0      TEGRA264_SID(0x0e)
+#define TEGRA264_SID_FSI0      TEGRA264_SID(0x0f)
+#define TEGRA264_SID_FSI1      TEGRA264_SID(0x10)
+#define TEGRA264_SID_PVA       TEGRA264_SID(0x11)
+#define TEGRA264_SID_SDMMC0    TEGRA264_SID(0x12)
+#define TEGRA264_SID_MGBE0     TEGRA264_SID(0x13)
+#define TEGRA264_SID_MGBE1     TEGRA264_SID(0x14)
+#define TEGRA264_SID_MGBE2     TEGRA264_SID(0x15)
+#define TEGRA264_SID_MGBE3     TEGRA264_SID(0x16)
+#define TEGRA264_SID_MSSSEQ    TEGRA264_SID(0x17)
+#define TEGRA264_SID_SE        TEGRA264_SID(0x18)
+#define TEGRA264_SID_SEU1      TEGRA264_SID(0x19)
+#define TEGRA264_SID_SEU2      TEGRA264_SID(0x1a)
+#define TEGRA264_SID_SEU3      TEGRA264_SID(0x1b)
+#define TEGRA264_SID_PSC       TEGRA264_SID(0x1c)
+#define TEGRA264_SID_OESP      TEGRA264_SID(0x23)
+#define TEGRA264_SID_SB        TEGRA264_SID(0x24)
+#define TEGRA264_SID_XSPI0     TEGRA264_SID(0x25)
+#define TEGRA264_SID_TSEC      TEGRA264_SID(0x29)
+#define TEGRA264_SID_UFS       TEGRA264_SID(0x2a)
+#define TEGRA264_SID_RCE       TEGRA264_SID(0x2b)
+#define TEGRA264_SID_RCE1      TEGRA264_SID(0x2c)
+#define TEGRA264_SID_VI        TEGRA264_SID(0x2e)
+#define TEGRA264_SID_VI1       TEGRA264_SID(0x2f)
+#define TEGRA264_SID_VIC       TEGRA264_SID(0x30)
+#define TEGRA264_SID_XUSB_DEV  TEGRA264_SID(0x32)
+#define TEGRA264_SID_XUSB_DEV1 TEGRA264_SID(0x33)
+#define TEGRA264_SID_XUSB_DEV2 TEGRA264_SID(0x34)
+#define TEGRA264_SID_XUSB_DEV3 TEGRA264_SID(0x35)
+#define TEGRA264_SID_XUSB_DEV4 TEGRA264_SID(0x36)
+#define TEGRA264_SID_XUSB_DEV5 TEGRA264_SID(0x37)
+
+/*
+ * memory client IDs
+ */
+
+/* HOST1X read client */
+#define TEGRA264_MEMORY_CLIENT_HOST1XR		0x16
+/* VIC read client */
+#define TEGRA264_MEMORY_CLIENT_VICR		0x6c
+/* VIC Write client */
+#define TEGRA264_MEMORY_CLIENT_VICW		0x6d
+/* VI R5 Write client */
+#define TEGRA264_MEMORY_CLIENT_VIW		0x72
+#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC	0x78
+#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC	0x79
+/* Audio processor(APE) Read client */
+#define TEGRA264_MEMORY_CLIENT_APER		0x7a
+/* Audio processor(APE) Write client */
+#define TEGRA264_MEMORY_CLIENT_APEW		0x7b
+/* Audio DMA Read client */
+#define TEGRA264_MEMORY_CLIENT_APEDMAR		0x9f
+/* Audio DMA Write client */
+#define TEGRA264_MEMORY_CLIENT_APEDMAW		0xa0
+#define TEGRA264_MEMORY_CLIENT_GPUR02MC		0xb6
+#define TEGRA264_MEMORY_CLIENT_GPUW02MC		0xb7
+/* VI Falcon Read client */
+#define TEGRA264_MEMORY_CLIENT_VIFALCONR	0xbc
+/* VI Falcon Write client */
+#define TEGRA264_MEMORY_CLIENT_VIFALCONW	0xbd
+/* Read Client of RCE */
+#define TEGRA264_MEMORY_CLIENT_RCER		0xd2
+/* Write client of RCE */
+#define TEGRA264_MEMORY_CLIENT_RCEW		0xd3
+/* PCIE0/MSI Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE0W		0xd9
+/* PCIE1/RPX4 Read clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE1R		0xda
+/* PCIE1/RPX4 Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE1W		0xdb
+/* PCIE2/DMX4 Read clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE2AR		0xdc
+/* PCIE2/DMX4 Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE2AW		0xdd
+/* PCIE3/RPX4 Read clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE3R		0xde
+/* PCIE3/RPX4 Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE3W		0xdf
+/* PCIE4/DMX8 Read clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE4R		0xe0
+/* PCIE4/DMX8 Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE4W		0xe1
+/* PCIE5/DMX4 Read clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE5R		0xe2
+/* PCIE5/DMX4 Write clients */
+#define TEGRA264_MEMORY_CLIENT_PCIE5W		0xe3
+/* UFS Read client */
+#define TEGRA264_MEMORY_CLIENT_UFSR		0x15c
+/* UFS write client */
+#define TEGRA264_MEMORY_CLIENT_UFSW		0x15d
+/* HDA Read client */
+#define TEGRA264_MEMORY_CLIENT_HDAR		0x17c
+/* HDA Write client */
+#define TEGRA264_MEMORY_CLIENT_HDAW		0x17d
+/* Disp ISO Read Client */
+#define TEGRA264_MEMORY_CLIENT_DISPR		0x182
+/* MGBE0 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE0R		0x1a2
+/* MGBE0 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE0W		0x1a3
+/* MGBE1 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE1R		0x1a4
+/* MGBE1 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_MGBE1W		0x1a5
+/* VI1 R5 Write client */
+#define TEGRA264_MEMORY_CLIENT_VI1W		0x1a6
+/* SDMMC0 Read mccif */
+#define TEGRA264_MEMORY_CLIENT_SDMMC0R		0x1c2
+/* SDMMC0 Write mccif */
+#define TEGRA264_MEMORY_CLIENT_SDMMC0W		0x1c3
+
+#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */
diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h
index 28ad0235086..af3fd388329 100644
--- a/include/dt-bindings/pinctrl/stm32-pinfunc.h
+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h
@@ -26,6 +26,7 @@
 #define AF14	0xf
 #define AF15	0x10
 #define ANALOG	0x11
+#define RSVD	0x12
 
 /* define Pins number*/
 #define PIN_NO(port, line)	(((port) - 'A') * 0x10 + (line))
diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h b/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h
new file mode 100644
index 00000000000..6b3d8ea7bb6
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_
+#define _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_
+
+#define PD_VE			0
+#define PD_GPU			1
+#define PD_VI			2
+#define PD_VO0			3
+#define PD_VO1			4
+#define PD_DE			5
+#define PD_NAND			6
+#define PD_PCIE			7
+
+#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ */
diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h
new file mode 100644
index 00000000000..bc9aba73c19
--- /dev/null
+++ b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_
+#define _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_
+
+#define PD_DSP			0
+#define PD_NPU			1
+#define PD_AUDIO		2
+#define PD_SRAM			3
+#define PD_RISCV		4
+
+#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ */
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index d9b7bac3095..f15bcee7c92 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -240,6 +240,7 @@
 #define RPMH_REGULATOR_LEVEL_TURBO_L2		432
 #define RPMH_REGULATOR_LEVEL_TURBO_L3		448
 #define RPMH_REGULATOR_LEVEL_TURBO_L4		452
+#define RPMH_REGULATOR_LEVEL_TURBO_L5		456
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO 	464
 #define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR	480
 
diff --git a/include/dt-bindings/power/rockchip,rk3528-power.h b/include/dt-bindings/power/rockchip,rk3528-power.h
new file mode 100644
index 00000000000..318923cdaaf
--- /dev/null
+++ b/include/dt-bindings/power/rockchip,rk3528-power.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__
+#define __DT_BINDINGS_POWER_RK3528_POWER_H__
+
+#define RK3528_PD_PMU		0
+#define RK3528_PD_BUS		1
+#define RK3528_PD_DDR		2
+#define RK3528_PD_MSCH		3
+
+/* VD_GPU */
+#define RK3528_PD_GPU		4
+
+/* VD_LOGIC */
+#define RK3528_PD_RKVDEC	5
+#define RK3528_PD_RKVENC	6
+#define RK3528_PD_VO		7
+#define RK3528_PD_VPU		8
+
+#endif
diff --git a/include/dt-bindings/regulator/nxp,pca9450-regulator.h b/include/dt-bindings/regulator/nxp,pca9450-regulator.h
new file mode 100644
index 00000000000..08434caef42
--- /dev/null
+++ b/include/dt-bindings/regulator/nxp,pca9450-regulator.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Device Tree binding constants for the NXP PCA9450A/B/C PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATORS_NXP_PCA9450_H
+#define _DT_BINDINGS_REGULATORS_NXP_PCA9450_H
+
+/*
+ * Buck mode constants which may be used in devicetree properties (eg.
+ * regulator-initial-mode, regulator-allowed-modes).
+ * See the manufacturer's datasheet for more information on these modes.
+ */
+
+#define PCA9450_BUCK_MODE_AUTO		0
+#define PCA9450_BUCK_MODE_FORCE_PWM	1
+
+#endif
diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/include/dt-bindings/regulator/st,stm32mp15-regulator.h
new file mode 100644
index 00000000000..7052507cb3e
--- /dev/null
+++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H
+#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H
+
+/* SCMI voltage domain identifiers */
+
+/* SOC Internal regulators */
+#define VOLTD_SCMI_REG11		0
+#define VOLTD_SCMI_REG18		1
+#define VOLTD_SCMI_USB33		2
+
+/* STPMIC1 regulators */
+#define VOLTD_SCMI_STPMIC1_BUCK1	3
+#define VOLTD_SCMI_STPMIC1_BUCK2	4
+#define VOLTD_SCMI_STPMIC1_BUCK3	5
+#define VOLTD_SCMI_STPMIC1_BUCK4	6
+#define VOLTD_SCMI_STPMIC1_LDO1		7
+#define VOLTD_SCMI_STPMIC1_LDO2		8
+#define VOLTD_SCMI_STPMIC1_LDO3		9
+#define VOLTD_SCMI_STPMIC1_LDO4		10
+#define VOLTD_SCMI_STPMIC1_LDO5		11
+#define VOLTD_SCMI_STPMIC1_LDO6		12
+#define VOLTD_SCMI_STPMIC1_VREFDDR	13
+#define VOLTD_SCMI_STPMIC1_BOOST	14
+#define VOLTD_SCMI_STPMIC1_PWR_SW1	15
+#define VOLTD_SCMI_STPMIC1_PWR_SW2	16
+#define VOLTD_SCMI_VREFBUF		17
+
+/* External regulators */
+#define VOLTD_SCMI_REGU0		18
+#define VOLTD_SCMI_REGU1		19
+#define VOLTD_SCMI_REGU2		20
+#define VOLTD_SCMI_REGU3		21
+#define VOLTD_SCMI_REGU4		22
+
+#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */
diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h
new file mode 100644
index 00000000000..e4f6612607f
--- /dev/null
+++ b/include/dt-bindings/reset/canaan,k230-rst.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
+ * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
+#define _DT_BINDINGS_CANAAN_K230_RST_H_
+
+#define RST_CPU0		0
+#define RST_CPU1		1
+#define RST_CPU0_FLUSH		2
+#define RST_CPU1_FLUSH		3
+#define RST_AI			4
+#define RST_VPU			5
+#define RST_HISYS		6
+#define RST_HISYS_AHB		7
+#define RST_SDIO0		8
+#define RST_SDIO1		9
+#define RST_SDIO_AXI		10
+#define RST_USB0		11
+#define RST_USB1		12
+#define RST_USB0_AHB		13
+#define RST_USB1_AHB		14
+#define RST_SPI0		15
+#define RST_SPI1		16
+#define RST_SPI2		17
+#define RST_SEC			18
+#define RST_PDMA		19
+#define RST_SDMA		20
+#define RST_DECOMPRESS		21
+#define RST_SRAM		22
+#define RST_SHRM_AXIM		23
+#define RST_SHRM_AXIS		24
+#define RST_NONAI2D		25
+#define RST_MCTL		26
+#define RST_ISP			27
+#define RST_ISP_DW		28
+#define RST_DPU			29
+#define RST_DISP		30
+#define RST_GPU			31
+#define RST_AUDIO		32
+#define RST_TIMER0		33
+#define RST_TIMER1		34
+#define RST_TIMER2		35
+#define RST_TIMER3		36
+#define RST_TIMER4		37
+#define RST_TIMER5		38
+#define RST_TIMER_APB		39
+#define RST_HDI			40
+#define RST_WDT0		41
+#define RST_WDT1		42
+#define RST_WDT0_APB		43
+#define RST_WDT1_APB		44
+#define RST_TS_APB		45
+#define RST_MAILBOX		46
+#define RST_STC			47
+#define RST_PMU			48
+#define RST_LOSYS_APB		49
+#define RST_UART0		50
+#define RST_UART1		51
+#define RST_UART2		52
+#define RST_UART3		53
+#define RST_UART4		54
+#define RST_I2C0		55
+#define RST_I2C1		56
+#define RST_I2C2		57
+#define RST_I2C3		58
+#define RST_I2C4		59
+#define RST_JAMLINK0_APB	60
+#define RST_JAMLINK1_APB	61
+#define RST_JAMLINK2_APB	62
+#define RST_JAMLINK3_APB	63
+#define RST_CODEC_APB		64
+#define RST_GPIO_DB		65
+#define RST_GPIO_APB		66
+#define RST_ADC			67
+#define RST_ADC_APB		68
+#define RST_PWM_APB		69
+#define RST_SHRM_APB		70
+#define RST_CSI0		71
+#define RST_CSI1		72
+#define RST_CSI2		73
+#define RST_CSI_DPHY		74
+#define RST_ISP_AHB		75
+#define RST_M0			76
+#define RST_M1			77
+#define RST_M2			78
+#define RST_SPI2AXI		79
+
+#endif
diff --git a/include/dt-bindings/reset/nvidia,tegra264.h b/include/dt-bindings/reset/nvidia,tegra264.h
new file mode 100644
index 00000000000..a61a56bb232
--- /dev/null
+++ b/include/dt-bindings/reset/nvidia,tegra264.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA264_H
+#define DT_BINDINGS_RESET_NVIDIA_TEGRA264_H
+
+#define TEGRA264_RESET_APE_TKE			1
+#define TEGRA264_RESET_CEC			2
+#define TEGRA264_RESET_ADSP_ALL			3
+#define TEGRA264_RESET_RCE_ALL			4
+#define TEGRA264_RESET_UFSHC			5
+#define TEGRA264_RESET_UFSHC_AXI_M		6
+#define TEGRA264_RESET_UFSHC_LP_SEQ		7
+#define TEGRA264_RESET_DPAUX			8
+#define TEGRA264_RESET_EQOS_PCS			9
+#define TEGRA264_RESET_HWPM			10
+#define TEGRA264_RESET_I2C1			11
+#define TEGRA264_RESET_I2C2			12
+#define TEGRA264_RESET_I2C3			13
+#define TEGRA264_RESET_I2C4			14
+#define TEGRA264_RESET_I2C6			15
+#define TEGRA264_RESET_I2C7			16
+#define TEGRA264_RESET_I2C8			17
+#define TEGRA264_RESET_I2C9			18
+#define TEGRA264_RESET_ISP			19
+#define TEGRA264_RESET_LA			20
+#define TEGRA264_RESET_NVCSI			21
+#define TEGRA264_RESET_EQOS_MAC			22
+#define TEGRA264_RESET_PWM10			23
+#define TEGRA264_RESET_PWM2			24
+#define TEGRA264_RESET_PWM3			25
+#define TEGRA264_RESET_PWM4			26
+#define TEGRA264_RESET_PWM5			27
+#define TEGRA264_RESET_PWM9			28
+#define TEGRA264_RESET_QSPI0			29
+#define TEGRA264_RESET_HDA			30
+#define TEGRA264_RESET_HDACODEC			31
+#define TEGRA264_RESET_I2C0			32
+#define TEGRA264_RESET_I2C10			33
+#define TEGRA264_RESET_SDMMC1			34
+#define TEGRA264_RESET_MIPI_CAL			35
+#define TEGRA264_RESET_SPI1			36
+#define TEGRA264_RESET_SPI2			37
+#define TEGRA264_RESET_SPI3			38
+#define TEGRA264_RESET_SPI4			39
+#define TEGRA264_RESET_SPI5			40
+#define TEGRA264_RESET_SPI7			41
+#define TEGRA264_RESET_SPI8			42
+#define TEGRA264_RESET_SPI9			43
+#define TEGRA264_RESET_TACH0			44
+#define TEGRA264_RESET_TSEC			45
+#define TEGRA264_RESET_VI			46
+#define TEGRA264_RESET_VI1			47
+#define TEGRA264_RESET_PVA0_ALL			48
+#define TEGRA264_RESET_VIC			49
+#define TEGRA264_RESET_MPHY_CLK_CTL		50
+#define TEGRA264_RESET_MPHY_L0_RX		51
+#define TEGRA264_RESET_MPHY_L0_TX		52
+#define TEGRA264_RESET_MPHY_L1_RX		53
+#define TEGRA264_RESET_MPHY_L1_TX		54
+#define TEGRA264_RESET_ISP1			55
+#define TEGRA264_RESET_I2C11			56
+#define TEGRA264_RESET_I2C12			57
+#define TEGRA264_RESET_I2C14			58
+#define TEGRA264_RESET_I2C15			59
+#define TEGRA264_RESET_I2C16			60
+#define TEGRA264_RESET_EQOS_MACSEC		61
+#define TEGRA264_RESET_MGBE0_PCS		62
+#define TEGRA264_RESET_MGBE0_MAC		63
+#define TEGRA264_RESET_MGBE0_MACSEC		64
+#define TEGRA264_RESET_MGBE1_PCS		65
+#define TEGRA264_RESET_MGBE1_MAC		66
+#define TEGRA264_RESET_MGBE1_MACSEC		67
+#define TEGRA264_RESET_MGBE2_PCS		68
+#define TEGRA264_RESET_MGBE2_MAC		69
+#define TEGRA264_RESET_MGBE2_MACSEC		70
+#define TEGRA264_RESET_MGBE3_PCS		71
+#define TEGRA264_RESET_MGBE3_MAC		72
+#define TEGRA264_RESET_MGBE3_MACSEC		73
+#define TEGRA264_RESET_ADSP_CORE0		74
+#define TEGRA264_RESET_ADSP_CORE1		75
+#define TEGRA264_RESET_APE			76
+#define TEGRA264_RESET_XUSB1_PADCTL		77
+#define TEGRA264_RESET_AON_CPU_ALL		78
+#define TEGRA264_RESET_AON_HSP			79
+#define TEGRA264_RESET_UART4			80
+#define TEGRA264_RESET_UART5			81
+#define TEGRA264_RESET_UART9			82
+#define TEGRA264_RESET_UART10			83
+#define TEGRA264_RESET_UART8			84
+
+#endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA264_H */
diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
index dd6fbb372e1..eb31ae9958d 100644
--- a/include/dt-bindings/reset/sun55i-a523-r-ccu.h
+++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h
@@ -21,5 +21,6 @@
 #define RST_BUS_R_IR_RX		12
 #define RST_BUS_R_RTC		13
 #define RST_BUS_R_CPUCFG	14
+#define RST_BUS_R_PPU0		15
 
 #endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */