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authorPrasad Kummari <prasad.kummari@amd.com>2025-02-28 14:47:24 +0530
committerTom Rini <trini@konsulko.com>2025-04-29 15:29:00 -0600
commitf59cb6a6970bd5603e225acabf741b930fd43156 (patch)
treed115cd83849799796c886f193b978622aafb16f8 /lib/efi_driver/efi_uclass.c
parentc0ed43c2a934dadc4066e3a1e62e4db43b2fbc20 (diff)
Revert "mtd: spi-nor: Remove recently added SST special case"
SST(sst26wf016) flashes have multiple erase block sizes, including 8 KB, 32 KB, and 64 KB. Since a 64 KB sector erase cannot be performed on all blocks, the 4 KB sector erase command should be used instead. Enabling the SPI_FLASH_USE_4K_SECTORS configuration allows the use of 4 KB sector erases, but it may increase the erase operation time for large memory flashes. This reverts commit 34cd4a72fb2d113e2754c0d643618a8e3fa549ab MEMORY ORGANIZATION: The SST26WF016B/016BA SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two 32 KByte overlay, and thirty 64 KByte overlay blocks. See Figure 3-1. Top of Memory Block ┌──────────┐ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 32 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 64 KByte │ ├──────────┤ │ 32 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ ├──────────┤ │ 8 KByte │ └──────────┘ Bottom of Memory Block ┌────────────────────────────────┐ │ 64 KByte │ ├────────────────────────────────┤ │ 64 KByte │ └────────────────────────────────┘ Expanded View: ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ │ 4 KB │ │ 4 KB │ │ 4 KB │ │ 4 KB │ ├──────┤ ├──────┤ ├──────┤ ├──────┤ │ . . . (continues) . . . │ └──────┘ └──────┘ └──────┘ └──────┘ 2 Sectors for 8 KByte blocks 8 Sectors for 32 KByte blocks 16 Sectors for 64 KByte blocks Link: https://ww1.microchip.com/downloads/en/DeviceDoc/20005013D.pdf Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Diffstat (limited to 'lib/efi_driver/efi_uclass.c')
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