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authorMarek Vasut <marex@denx.de>2024-12-29 21:53:26 +0100
committerTom Rini <trini@konsulko.com>2025-01-30 19:28:33 -0600
commit487b254702858a69f96d0c314ab1eab66ac084e2 (patch)
tree90b43c51074b7ae89c4428e4657208342f87948c /lib/string.c
parentac3eeb154257f422d87c3e4ad5414c350238c3b9 (diff)
net: phy: Add RGMII RX/TX delay handling to DP83822 PHY
The TI DP83822 does have support for configurable RGMII RX/TX clock shift, add support for parsing DT properties which describe the RX/TX clock shift configuration and configuration of the matching bits in RCSR register. The shift is only configurable on DP83822, the other PHYs supported by this PHY driver, namely DP83825/DP83826 variants, do not implement this functionality and the RCSR bits used to configure the clock shift are missing from those PHYs. The shift is configurable separately for RX and TX path. Each path can either enable the shift or disable the shift using single bit. In case the shift is disabled, a delay of 0ns is added to the path, otherwise a delay of 3.5ns is added to the path. Note that the two RCSR bits 11 and 12 have inverted logic, RCSR bit 12 enables RX internal shift when SET, while RCSR bit 11 enables TX shift when UNSET. Signed-off-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'lib/string.c')
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