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| author | Torsten Duwe <duwe@lst.de> | 2023-08-14 18:05:33 +0200 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-09-05 10:53:36 +0800 |
| commit | 6164d86984cb6246680e5d94d9ec0633f2b70e98 (patch) | |
| tree | 6f46d4b8d5e9cad5f969665f707d0b7374ef9130 /lib/zstd/common/mem.h | |
| parent | f39f8f77a5268530e982aa38e921c640d532a9ae (diff) | |
riscv: jh7110: enable riscv,timer in the device tree
The JH7110 has the arhitectural CPU timer on all 5 rv64 cores.
Note that in the device tree.
Signed-off-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'lib/zstd/common/mem.h')
0 files changed, 0 insertions, 0 deletions