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authorXingyu Wu <xingyu.wu@starfivetech.com>2023-07-07 18:50:08 +0800
committerLeo Yu-Chi Liang <ycliang@andestech.com>2023-07-24 13:21:01 +0800
commit005f9627d02e8ecab3c58c77889060e72f7fa25d (patch)
treeb63fe4485552248aba0081de015f913ddd4c1243 /lib
parent2d7a5787915716040ec381d1cf5064a3401ed12a (diff)
riscv: dts: jh7110: Add PLL clock controller node
Add child node about PLL clock controller in sys_syscon node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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