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authorTom Rini <trini@konsulko.com>2019-05-05 12:25:39 -0400
committerTom Rini <trini@konsulko.com>2019-05-05 12:25:39 -0400
commitabad176da14c576b5126484b03cba73a3b2c6f16 (patch)
tree1baba7f9058acf8e41a043e6ce0f08dd1b94f644 /test/dm/cache.c
parent86f578ee85a697afb980233312f9aac1d98816df (diff)
parent9337a08768dfa0a006382f1d05cf69b5f67f7844 (diff)
Merge branch '2019-05-05-master-imports'
- Various assorted fixes - btrfs zstd compression support - Enable hardware DDR levelling on am43xx platforms. - pl310 cache controller driver
Diffstat (limited to 'test/dm/cache.c')
-rw-r--r--test/dm/cache.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/test/dm/cache.c b/test/dm/cache.c
new file mode 100644
index 00000000000..d4144aab76f
--- /dev/null
+++ b/test/dm/cache.c
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/test.h>
+
+static int dm_test_reset(struct unit_test_state *uts)
+{
+ struct udevice *dev_cache;
+ struct cache_info;
+
+ ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
+ ut_assertok(cache_get_info(dev, &info));
+
+ return 0;
+}
+DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);