diff options
author | Tom Rini <trini@konsulko.com> | 2020-10-05 10:54:27 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2020-10-05 10:54:27 -0400 |
commit | caebff09efe8c061b4d99b82262c67fb2db9bbcf (patch) | |
tree | 24fcdb0737bea1d87c0a36f7eb371017af83e5c2 /test/dm/clk_ccf.c | |
parent | 17e76b33cc0ec2eb2c519b66b6f6c491718e8046 (diff) | |
parent | 01c35f269f21398fa9d1db1b90b73f7e95a3bf22 (diff) |
Merge tag 'u-boot-atmel-2021.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for 2021.01 cycle:
This feature set includes a new CPU driver for at91 family, new driver
for PIT64B hardware timer, support for new at91 family SoC named sama7g5
which adds: clock support, including conversion of the clock tree to
CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The
feature set also includes updates for mmc driver and some other minor
fixes and features regarding building without the old Atmel PIT and the
possibility to read a secondary MAC address from a second i2c EEPROM.
Diffstat (limited to 'test/dm/clk_ccf.c')
-rw-r--r-- | test/dm/clk_ccf.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c index 32bc4d2b8a0..e4ebb93cdad 100644 --- a/test/dm/clk_ccf.c +++ b/test/dm/clk_ccf.c @@ -22,6 +22,10 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) struct udevice *dev; long long rate; int ret; +#if CONFIG_IS_ENABLED(CLK_CCF) + const char *clkname; + int clkid, i; +#endif /* Get the device using the clk device */ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev)); @@ -130,6 +134,59 @@ static int dm_test_clk_ccf(struct unit_test_state *uts) ret = sandbox_clk_enable_count(pclk); ut_asserteq(ret, 0); + + /* Test clock re-parenting. */ + ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk); + ut_assertok(ret); + ut_asserteq_str("usdhc1_sel", clk->dev->name); + + pclk = clk_get_parent(clk); + ut_assertok_ptr(pclk); + if (!strcmp(pclk->dev->name, "pll3_60m")) { + clkname = "pll3_80m"; + clkid = SANDBOX_CLK_PLL3_80M; + } else { + clkname = "pll3_60m"; + clkid = SANDBOX_CLK_PLL3_60M; + } + + ret = clk_get_by_id(clkid, &pclk); + ut_assertok(ret); + ret = clk_set_parent(clk, pclk); + ut_assertok(ret); + pclk = clk_get_parent(clk); + ut_assertok_ptr(pclk); + ut_asserteq_str(clkname, pclk->dev->name); + + /* Test disabling critical clock. */ + ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk); + ut_assertok(ret); + ut_asserteq_str("i2c_root", clk->dev->name); + + /* Disable it, if any. */ + ret = sandbox_clk_enable_count(clk); + for (i = 0; i < ret; i++) { + ret = clk_disable(clk); + ut_assertok(ret); + } + + ret = sandbox_clk_enable_count(clk); + ut_asserteq(ret, 0); + + clk->flags = CLK_IS_CRITICAL; + ret = clk_enable(clk); + ut_assertok(ret); + + ret = clk_disable(clk); + ut_assertok(ret); + ret = sandbox_clk_enable_count(clk); + ut_asserteq(ret, 1); + clk->flags &= ~CLK_IS_CRITICAL; + + ret = clk_disable(clk); + ut_assertok(ret); + ret = sandbox_clk_enable_count(clk); + ut_asserteq(ret, 0); #endif return 1; |