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| author | Tom Rini <trini@konsulko.com> | 2025-02-25 08:25:00 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:54:05 -0600 |
| commit | 4da90796ca8bde2171cdd5bb7d1293b1edbccab6 (patch) | |
| tree | 237b788e27beb6337b87113510a47e34fb85e686 /test/py/spawn.py | |
| parent | 3ecda19009ebbe46a64b0629f8b64173c7a551c0 (diff) | |
| parent | 7965e52e32b0acd561c09f12c4aac1d075c16622 (diff) | |
Merge tag 'u-boot-socfpga-next-20250225' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
CI: https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/24816
Please pull the SoCFPGA changes for next from u-boot-socfpga, containing
boot support for the Altera SoCFPGA Agilex 5 platform in U-Boot. The
changes include:
1. Board-specific configurations and setup required to enable Agilex 5
operation in U-Boot.
2. Integration of cache coherency unit (CCU) initialization routine,
including CCU conguration in DT.
3. Clock, firewall (configured in DT), SMMU, low level initialization
specific to Agilex 5.
4. Integration of memory initialization routine, including DDR setup.
This patch set has been tested on Agilex 5 devkit with QSPI boot
(UBI/UBIFS) and RAM boot (TFTP & ARM DS debugger).
Diffstat (limited to 'test/py/spawn.py')
0 files changed, 0 insertions, 0 deletions