diff options
| author | Giulio Benetti <giulio.benetti@benettiengineering.com> | 2020-04-08 17:10:07 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-04-18 12:54:43 +0200 |
| commit | 8cefbe98b16e756b886ebcbe77ba66e05b9392b4 (patch) | |
| tree | a98df4f6e9bc3d893e7a9625e38f7377d40370b0 /test/py/tests/test_bind.py | |
| parent | a5ed4fa95f870d5b1aa4437f1dc9e65f69a58805 (diff) | |
clk: imx: pllv3: add enable_bit
pllv3 PLLs have powerdown/up bits but enable bits too. Specifically
"enable bit" enable the pll output, so when dis/enabling pll by
setting/clearing power_bit we must also set/clear enable_bit.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Diffstat (limited to 'test/py/tests/test_bind.py')
0 files changed, 0 insertions, 0 deletions