Merge tag 'xilinx-for-v2022.10-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.10-rc2

fpga:
- Convert SYS_FPGA_CHECK_CTRLC and SYS_FPGA_PROG_FEEDBACK to Kconfig
- Add support for secure bitstream loading

spi:
- xilinx_spi: Add support for memopers and supports_op
- zynq_qspi: Add support for supports_op/child_pre_probe
- zynq_qspi: Fix dummy cycle and qspi speed calculations

xilinx:
- Get rid of #stream-id-cells
- Use fixed partitions for SOM
- Add support for UUID reading from FRU
- Use strlcpy instead of strncpy
- Add reset driver support for ZynqMP and Versal
- Enable power domain driver in ZynqMP and Versal

zynqmp:
- Do no place BSS at 0 which have issue with NULL pointer
- Enable SLG gpio driver
- Disable LMB for mini configurations
- Remove duplicate PMIO_NODE_ID_BASE macro

versal:
- Add xlnx-versal-resets.h header

mmc:
- zynq_sdhci: Fix macro for MMC HS

relocate-rela:
- Fix support for BE hosts
- Define all macros for e_machine and reloc types

misc:
- Get rid of guard macros from ARM and RISC-V

lmb:
- Add support for disabling LMB

serial:
- zynq: Fix baudrate calculation

tests:
- Mark bind tests to run only on sandbox
- List also dm uclass and devres

1 files changed, 2 insertions, 1 deletions

diff --git a/test/py/tests/test_bind.py b/test/py/tests/test_bind.py
index d7e6626d45f..c90c54d266f 100644
--- a/test/py/tests/test_bind.py
+++ b/test/py/tests/test_bind.py
@@ -25,7 +25,7 @@ def in_tree(response, name, uclass, drv, depth, last_child):
             return True
     return False
 
-
+@pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_bind')
 def test_bind_unbind_with_node(u_boot_console):
 
@@ -117,6 +117,7 @@ def get_next_line(tree, name):
             break
     return child_line
 
+@pytest.mark.boardspec('sandbox')
 @pytest.mark.buildconfigspec('cmd_bind')
 def test_bind_unbind_with_uclass(u_boot_console):
     #bind /bind-test