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author | Jonas Karlman <jonas@kwiboo.se> | 2025-05-10 15:32:01 +0000 |
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committer | Tom Rini <trini@konsulko.com> | 2025-05-12 08:04:51 -0600 |
commit | 128d997a8772cc174f38d529d8b25f90b3aa8ad8 (patch) | |
tree | f04b3ccac477eb066581d42f957cefa97f435981 /test/py/tests/test_fpga.py | |
parent | fa51a4d57d910df4f3beffa5d3e1d61a1d5d824b (diff) |
clk: Fix clk_set_parent() regression
The commit ac30d90f3367 ("clk: Ensure the parent clocks are enabled
while reparenting") add a call to clk_enable() for the parent clock.
For clock drivers that do not implement the enable() ops, like most
Rockchip clock drivers, this now cause the set_parent() ops to never
be called when CLK_CCF=n (default for Rockchip).
clk_enable() typically return -ENOSYS when the enable() ops is not
implemented by the clock driver, with CLK_CCF=y clk_enable() instead
return 0 when the enable() ops is unimplemented.
Change to ignore -ENOSYS from the newly introduced clk_enable() call to
fix this regression and restore the old behavior of set_parent() ops
being called regardless of if enable() ops is implemented or not.
Fixes: ac30d90f3367 ("clk: Ensure the parent clocks are enabled while reparenting")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Tested-by: Dang Huynh <danct12@riseup.net>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'test/py/tests/test_fpga.py')
0 files changed, 0 insertions, 0 deletions