Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblaze

Xilinx/FPGA changes for v2019.07

fpga:
- Add support for external data in FIT
- Extend testing for external data case
- Inform user about a need to run post config on Zynq

arm:
- Tune zynq command functions
- Fix internal variable setting

arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case

spi:
- Fix tap delay programming

clk:
- Enable i2c in SPL

net:
- Fix gem phydev handling
- Remove phy detection code from gem driver

general:
- Correct EXT_DTB usage for MULTI_DTB_FIT configuration

1 files changed, 13 insertions, 0 deletions

diff --git a/test/py/tests/test_fpga.py b/test/py/tests/test_fpga.py
index 798f6eed3dc..e3bb7b41c74 100644
--- a/test/py/tests/test_fpga.py
+++ b/test/py/tests/test_fpga.py
@@ -357,6 +357,19 @@ def test_fpga_loadmk_legacy_gz(u_boot_console):
 @pytest.mark.buildconfigspec('cmd_fpga_loadmk')
 @pytest.mark.buildconfigspec('fit')
 @pytest.mark.buildconfigspec('cmd_echo')
+def test_fpga_loadmk_fit_external(u_boot_console):
+    f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit_external')
+
+    u_boot_console.run_command('imi %x' % (addr))
+
+    expected_text = 'FPGA loaded successfully'
+    output = u_boot_console.run_command('fpga loadmk %x %x:fpga && echo %s' % (dev, addr, expected_text))
+    assert expected_text in output
+
+@pytest.mark.buildconfigspec('cmd_fpga')
+@pytest.mark.buildconfigspec('cmd_fpga_loadmk')
+@pytest.mark.buildconfigspec('fit')
+@pytest.mark.buildconfigspec('cmd_echo')
 def test_fpga_loadmk_fit(u_boot_console):
     f, dev, addr, bit, bit_size = load_file_from_var(u_boot_console, 'mkimage_fit')