diff options
author | Dylan Hung <dylan_hung@aspeedtech.com> | 2022-11-11 15:30:07 +0800 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-11-24 16:25:58 -0500 |
commit | bd1e1954216a54b1916e932512ee37c7d6a22e58 (patch) | |
tree | a2f8fc6b49c297aafa2877d3dea1f71f260fe976 /test/py/tests/test_source.py | |
parent | 581df347dbc3f5b528be8b36a62372c0aadde30a (diff) |
ram: ast2600: Improve ddr4 timing and signal quality
Adjust the following settings to get better timing and signal quality.
1. write DQS/DQ delay
- 1e6e2304[0]
- 1e6e2304[15:8]
2. read DQS/DQ delay
- 0x1e6e0298[0]
- 0x1e6e0298[15:8]
3. CLK/CA timing
- 0x1e6e01a8[31]
4. Read and write termination
- change RTT_ROM from 40 ohm to 48 ohm (MR1[10:8])
- change RTT_PARK from disable to 48 ohm (MR5[8:6])
- change RTT_WR from 120 ohm to disable (MR2[11:9])
- change PHY ODT from 40 ohm to 80 ohm (0x1e6e0130[10:8])
Note1: Both DDR-PHY and DDR controller have their own registers for DDR4
Mode Registers (MR0~MR6). This patch introduces macros to synchronize
the MR value on both sides.
Note2: the waveform meansurement can be found in item #21 of Aspeed
AST26x0 Application note (AP note).
Review-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Diffstat (limited to 'test/py/tests/test_source.py')
0 files changed, 0 insertions, 0 deletions