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| author | Varshini Rajendran <varshini.rajendran@microchip.com> | 2025-06-03 10:35:50 +0530 |
|---|---|---|
| committer | Eugen Hristev <eugen.hristev@linaro.org> | 2025-06-19 13:56:43 +0300 |
| commit | 107cf34bd799b868f3ec640d31567cd4a9bf7b81 (patch) | |
| tree | 713521c50c5a031ecec350f9d7318a42a6c7b39c /test/py/u_boot_utils.py | |
| parent | 02217d07a3e422203f0e142b095987582e0078e3 (diff) | |
clk: at91: sam9x60-pll: add support for HW PLL freq dividers
Add support for hardware dividers for PLL IDs.In sam9x7 SoC,
PLL_ID_PLLA and PLL_ID_PLLA_DIV2 has /2 hardware dividers
each.
fcorepllack -----> HW Div = 2 -+--> fpllack
|
+--> HW Div = 2 ---> fplladiv2ck
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Diffstat (limited to 'test/py/u_boot_utils.py')
0 files changed, 0 insertions, 0 deletions