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| author | Yao Zi <ziyao@disroot.org> | 2025-06-06 04:28:01 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-07-03 16:14:13 +0800 |
| commit | 5afad3d4a314464af34f9c312d3028b9053f1135 (patch) | |
| tree | 9413ed764b07060fba3fe138eb64bc6506cf3643 /test/py/u_boot_utils.py | |
| parent | 4153ceb0fe4f8c866e45fbf149cebb05f0f8405f (diff) | |
riscv: cpu: th1520: Setup CPU feature CSRs in harts_early_init
C910 cores integrated in TH1520 SoC provide various customized CSRs for
configuring core behavior, including cache coherency and timing, branch
predication, and clock gating for internal components.
This patch sets them up for efficient operation and satisfying
requirements of an SMP system.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'test/py/u_boot_utils.py')
0 files changed, 0 insertions, 0 deletions