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authorMikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>2025-07-09 12:28:09 +0300
committerTom Rini <trini@konsulko.com>2025-07-15 09:56:01 -0600
commit997786bbf473b3567bea5fa7ead21a8a9299c2ee (patch)
treeb5b1703089b2879e35913643c34d9abe19402db6 /test/py/u_boot_utils.py
parent5d49fa9e56bb0e0b085f5c794ba508349385f6b8 (diff)
drivers/net/airoha_eth: fix stalling in package receiving
ARCH_DMA_MINALIGN is 64 for ARMv7a/ARMv8a architectures, but RX/TX descriptors are 32 bytes long. So they may not be aligned on an ARCH_DMA_MINALIGN boundary. In case of RX path, this may cause the following problem 1) Assume that a packet has arrived and the EVEN rx descriptor has been updated with the incoming data. The driver will invalidate and check the corresponding rx descriptor. 2) Now suppose the next descriptor (ODD) has not yet completed. Please note that all even descriptors starts on 64-byte boundary, and the odd ones are NOT aligned on 64-byte boundary. Inspecting even descriptor, we will read the entire CPU cache line (64 bytes). So we read and sore in CPU cache also the next (odd) descriptor. 3) Now suppose the next packet (for the odd rx descriptor) arrived while the first packet was being processed. So we have new data in memory but old data in cache. 4) After packet processing (in arht_eth_free_pkt() function) we will cleanup the descriptor and put it back to rx queue. This will call flush_dcache_range() function for the even descriptor, so the odd one will be flushed as well (it is in the same cache line). So the old data will be written to the next rx descriptor. 5) We get a freeze. The next descriptor is empty (so the driver is waiting for packets), but the hardware will continue to receive packets on other available descriptors. This will continue until the last available rx descriptor is full. Then the hardware will also freeze. The problem will be solved if the previous descriptor will be put back to the queue instead of the current one. If the current descriptor is even (starts on a 64-byte boundary), then putting the previous descriptor to the rx queue will affect the previous cache line. To be 100% ok, we must make sure that the previous and the one before the previous descriptor cannot be used for receiving at this moment. If the current descriptor is odd, then the previous descriptor is on the same cache line. Both (current and previous) descriptors are not currently in use, so issue will not arrise. WARNING: The following restrictions on PKTBUFSRX must be held: * PKTBUFSRX is even, * PKTBUFSRX >= 4. The bug appears on 32-bit airoha platform, but should be present on 64-bit as well. The code was tested both on 32-bit and 64-bit airoha boards. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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