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| author | Chanho Park <chanho61.park@samsung.com> | 2023-10-31 17:56:00 +0900 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-11-02 15:44:56 +0800 |
| commit | b8a902b81462a1fa6bd4fc8614cdc386fa7849d4 (patch) | |
| tree | 824611f9f9ebba35e11fa4a43ffccc6037588d59 /tools/binman/cbfs_util_test.py | |
| parent | 37c2faf3252e8423be0577bed1358bd6f59b4c10 (diff) | |
board: starfive: spl: Support jtag for VisionFive2 board
JTAG pins are mapped as below. To access the JTAG pins, we need to
control the GPIO pins from SPL which seems to be the earliest stage for
JTAG.
- JTAG nTRST: GPIO36 / Input
- JTAG TDI: GPIO61 / Input
- JTAG TMS: GPIO63 / Input
- JTAG TCK: GPIO60 / Input
- JTAG TDO: GPIO44 / Output
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'tools/binman/cbfs_util_test.py')
0 files changed, 0 insertions, 0 deletions