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| author | Tom Rini <trini@konsulko.com> | 2025-02-03 08:24:49 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-03 08:24:49 -0600 |
| commit | 752321b62530dcbd6e8b5872aff4cf761809d76b (patch) | |
| tree | bb98312358819d96cac0a5f0af8092133d44fafb /tools/u_boot_pylib/command.py | |
| parent | 2b1c8d3b2da46ce0f7108f279f04bc66f1d8d09a (diff) | |
| parent | faf237d1b43c3221e78bfa0310833fc5bc71bc21 (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/24428
- RISC-V: Add some fixes
- RISC-V: Integrate OP-TEE into the RISC-V boot flow
- RISC-V: Unify implementation of cleanup_before_linux() for RISC-V
ports
- RISC-V: cmd: Add bhyve SBI implementation ID
- Board: K1: Probe dram size during boot phase
Diffstat (limited to 'tools/u_boot_pylib/command.py')
0 files changed, 0 insertions, 0 deletions