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| author | Tien Fong Chee <tien.fong.chee@intel.com> | 2024-08-14 15:56:25 +0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-02-25 10:54:01 -0600 |
| commit | b005eca0c91ce1b0136f4ac088fb98b7d93bbb51 (patch) | |
| tree | c0d8d9aea57ce83928ef64249add003ce3405454 /tools/u_boot_pylib/gitutil.py | |
| parent | 04ea9147d5bdab1370ced118acf35db7ac9e281c (diff) | |
arm: socfpga: agilex5: Add SPL for Agilex5 SoCFPGA
Add SPL support for Agilex5 SoCFPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/gitutil.py')
0 files changed, 0 insertions, 0 deletions