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authorWeijie Gao <weijie.gao@mediatek.com>2025-05-23 17:26:02 +0800
committerTom Rini <trini@konsulko.com>2025-06-05 14:30:35 -0600
commit6952209ef220138189dd261d06441e1b2d50e994 (patch)
tree965c283f3463eff0ad86f996cb578ad617e5def4 /tools/u_boot_pylib/terminal.py
parent6e15d3f91aa698798578d39a6d9e292fcc5c577f (diff)
serial: mediatek: enable baudrate accuracy compensation
The high-speed UART from MediaTek supports baudrate accuracy compensation when using high-speed mode 3. This is done by calculating the first digit of the fraction part of sample count value. The fraction value will be then used as the reference to insert 0 to 10 sample cycle(s) to one frame (assume that frame format is 8n1, i.e. 10 bits per frame). The fracdiv_[l/m] registers are used to determine whether a bit in one frame should be inserted with one sample cycle. With typical 40MHz source clock, the actual baudrates with/without accuracy compensation are: Ideal w/o compensation w/ compensation ======== ================ =============== 9600 9603 9600 115200 114942 115207 921600 930232 921659 3000000 3076923 3007519 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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