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| author | Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> | 2025-03-03 21:06:43 -0800 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:40 +0800 |
| commit | 1aa1022780c42e9835069b3005df60d578658b34 (patch) | |
| tree | a05421926b856c96269383dc2aee5e9a96c9cb05 /tools/u_boot_pylib/test_util.py | |
| parent | d13b1bbbde8f286fade80b50fd6645b869550de6 (diff) | |
arch: arm: dts: Enable kernel itb file generation for Agilex5 SoCFPGA
Load and entry addresses are corrected for Agilex5 SoCFPGA board
which would enable to generate the kernel itb file with the right
addresses.
Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions