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| author | Tom Rini <trini@konsulko.com> | 2025-04-17 07:52:02 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-04-17 07:52:02 -0600 |
| commit | 278be62c052f3a5749c3c7a57bcd307b82dcdc2d (patch) | |
| tree | dcb621d8d29086f3a0cdef7148f13ce32ebb7fb1 /tools/u_boot_pylib/test_util.py | |
| parent | 0f7a4ac96b27fa77b798c6c9598e05cf1654920b (diff) | |
| parent | 8e25e76fff0698c8268b279af3d7859ed2e14ea5 (diff) | |
Merge tag 'xilinx-for-v2025.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2025.07-rc1
AMD/Xilinx:
- Synchronize enums around tcm_mode
- Access bootmode registers via firmware interface
- Setup default values for DEBUG_UART
- Fix dfu alt buffer clearing
- Convert loadpdi command to fpga
- Fix board detection code
- Minor defconfig updates
Versal:
- Wire multi_boot register
Versal Gen 2:
- Enable missing drivers
- Wire i2c FRU decoding at start
- Wire saving variables to different locations
- Disable default DEBUG_UART
- Wire USB/UFS boot and fix access via firmware interface
- Minor fixes
ZynqMP/Kria:
- Enable mkfwumdata
- Topic board update
- Enhance binman configurations
- Kria usb update
BuR:
- Add multiple Zynq based boards
cadence_ospi:
- Enable device reset
fpga:
- Add support for loading bitstream for Altera SoCs
Diffstat (limited to 'tools/u_boot_pylib/test_util.py')
0 files changed, 0 insertions, 0 deletions